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ds099 july 13 , 2004 www.xilinx.com advance product specification 1-800-255-7778 ? 2003-2004 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. this document includes all four modules of the spartan?-3 fpga data sheet. module 1: introduction and ordering information ds099-1 (v1.2) december 24, 2003 6pages introduction features architectural overview product availability user i/o chart ordering information module 2: functional description ds099-2 (v1.2) july 11, 2003 40 pages iobs - iob overview - selectio? signal standards clb overview block ram dedicated multipliers digital clock manager (dcm) - clock network configuration module 3: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 40 pages dc electrical characteristics - absolute maximum ratings - supply voltage specifications - recommended operating conditions - dc characteristics switching characteristics - i/o timing - core logic timing - dcm timing - configuration and jtag timing module 4: pinout descriptions ds099-4 (v1. 5 ) july 13 , 2004 106 pages pin descriptions - pin behavior during configuration package overview pinout tables -footprints important note: the spartan-3 fpga data sheet is created and published in separate modules. this complete version is provided for easy downloading and searching of the complete document. page, figure, and table numbers begin at 1 for each module, and each module has its own revision history at the end. use the pdf "bookmarks" for easy navigation in this volume. 0 spartan-3 fpga family: complete data sheet ds099 july 13 , 2004 00 advance product specification r
ds099-1 (v1.2) december 24, 2003 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. introduction the spartan?-3 family of field-programmable gate arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. the eight-member family offers densities ranging from 50,000 to five million system gates, as shown in ta b l e 1 . the spartan-3 family builds on the success of the earlier spartan-iie family by increasing the amount of logic resources, the capacity of internal ram, the total number of i/os, and the overall level of performance as well as by improving clock management functions. numerous enhancements derive from state-of-the-art virtex?-ii tech- nology. these spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, set- ting new standards in the programmable logic industry. because of their exceptionally low cost, spartan-3 fpgas are ideally suited to a wide range of consumer electronics applications, including broadband access, home network- ing, display/projection and digital television equipment. the spartan-3 family is a superior alternative to mask pro- grammed asics. fpgas avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional asics. also, fpga programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with asics. features revolutionary 90-nanometer process technology very low cost, high-performance logic solution for high-volume, consumer-oriented applications - densities as high as 74,880 logic cells - 326 mhz system clock rate - three power rails: for core (1.2v), i/os (1.2v to 3.3v), and auxiliary purposes (2.5v) selectio? signaling - up to 784 i/o pins - 622 mb/s data transfer rate per i/o - seventeen single-ended signal standards - seven differential signal standards including lvds - termination by digitally controlled impedance - signal swing ranging from 1.14v to 3.45v - double data rate (ddr) support logic resources - abundant logic cells with shift register capability - wide multiplexers - fast look-ahead carry logic - dedicated 18 x 18 multipliers - jtag logic compatible with ieee 1149.1/1532 specifications selectram? hierarchical memory - up to 1,872 kbits of total block ram - up to 520 kbits of total distributed ram digital clock manager (up to four dcms) - clock skew elimination - frequency synthesis - high resolution phase shifting eight global clock lines and abundant routing fully supported by xilinx ise development system - synthesis, mapping, placement and routing microblaze processor, pci, and other cores 06 spartan-3 fpga family: introduction and ordering information ds099-1 (v1.2) december 24, 2003 00 advance product specification r table 1: summary of spartan-3 fpga attributes device system gates logic cells clb array (one clb = four slices) distributed ram (bits 1 ) block ram (bits 1 ) dedicated multipliers dcms maximum user i/o maximum differential i/o pairs rows columns total clbs xc3s50 50k 1,728 16 12 192 12k 72k 4 2 124 56 xc3s200 200k 4,320 24 20 480 30k 216k 12 4 173 76 xc3s400 400k 8,064 32 28 896 56k 288k 16 4 264 116 xc3s1000 1m 17,280 48 40 1,920 120k 432k 24 4 391 175 xc3s1500 1.5m 29,952 64 52 3,328 208k 576k 32 4 487 221 xc3s2000 2m 46,080 80 64 5,120 320k 720k 40 4 565 270 xc3s4000 4m 62,208 96 72 6,912 432k 1,728k 96 4 712 312 xc3s5000 5m 74,880 104 80 8,320 520k 1,872k 104 4 784 344 notes: 1. by convention, one kb is equivalent to 1,024 bits.
spartan-3 fpga family: introduction and ordering information 2 www.xilinx.com ds099-1 (v1.2) december 24, 2003 1-800-255-7778 advance product specification 6 r architectural overview the spartan-3 family architecture consists of five funda- mental programmable functional elements: configurable logic blocks (clbs) contain ram-based look-up tables (luts) to implement logic and storage elements that can be used as flip-flops or latches. clbs can be programmed to perform a wide variety of logical functions as well as to store data. input/output blocks (iobs) control the flow of data between the i/o pins and the internal logic of the device. each iob supports bidirectional data flow plus 3-state operation. twenty-four different signal standards, including seven high-performance differential standards, are available as shown in ta b l e 2 . double data-rate (ddr) registers are included. the digitally controlled impedance (dci) feature provides automatic on-chip terminations, simplifying board designs. block ram provides data storage in the form of 18-kbit dual-port blocks. multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. digital clock manager (dcm) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. these elements are organized as shown in figure 1 . a ring of iobs surrounds a regular array of clbs. the xc3s50 has a single column of block ram embedded in the array. those devices ranging from the xc3s200 to the xc3s2000 have two columns of block ram. the xc3s4000 and xc3s5000 devices have four ram columns. each column is made up of several 18k-bit ram blocks; each block is associated with a dedicated multiplier. the dcms are posi- tioned at the ends of the outer block ram columns. the spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. each functional element has an associated switch matrix that permits multiple con- nections to the routing. figure 1: spartan-3 family architecture ds099-1_01_032703 notes: 1. the two additional block ram columns of the xc3s4000 and xc3s5000 devices are shown with dashed lines. the xc3s50 has only the block ram column on the far left.
spartan-3 fpga family: introduction and ordering information ds099-1 (v1.2) december 24, 2003 www.xilinx.com 3 advance product specification 1-800-255-7778 r configuration spartan-3 fpgas are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. before pow- ering on the fpga, configuration data is stored externally in a prom or some other nonvolatile medium either on or off the board. after applying power, the configuration data is written to the fpga using any of five different modes: mas- ter parallel, slave parallel, master serial, slave serial and boundary scan (jtag). the master and slave parallel modes use an 8-bit wide selectmap? port. the recommended memory for storing the configuration data is the low-cost xilinx platform flash prom family, which includes the xcf00s proms for serial configuration and the higher density xcf00p proms for parallel or serial configuration. i/o capabilities the selectio feature of spartan-3 devices supports 17 sin- gle-ended standards and seven differential standards as listed in ta b l e 2 . many standards support the dci feature, which uses integrated terminations to eliminate unwanted signal reflections. ta b l e 3 shows the number of user i/os as well as the number of differential i/o pairs available for each device/package combination. table 2: signal standards supported by the spartan-3 family standard category description v cco (v) class symbol dci option single-ended gtl gunning transceiver logic n/a terminated gtl yes plus gtlp yes hstl high-speed transceiver logic 1.5 i hstl_i yes iii hstl_iii yes 1.8 i hstl_i_18 yes ii hstl_ii_18 yes iii hstl_iii_18 yes lvcmos low-voltage cmos 1.2 n/a lvcmos12 no 1.5 n/a lvcmos15 yes 1.8 n/a lvcmos18 yes 2.5 n/a lvcmos25 yes 3.3 n/a lvcmos33 yes lvttl low-voltage transistor-transistor logic 3.3 n/a lvttl no pci peripheral component interconnect 3.0 33 mhz pci33_3 no sstl stub series terminated logic 1.8 n/a sstl18_i yes 2.5 i sstl2_i yes ii sstl2_ii yes differential ldt lightning data transport (hypertransport?) 2.5 n/a ldt_25 no lvds low-voltage differential signaling standard lvds_25 yes bus blvds_25 no extended mode lvdsext_25 yes ultra ulvds_25 no lvpecl low-voltage positive emitter-coupled logic 2.5 n/a lvpecl_25 no rsds reduced-swing differential signaling 2.5 n/a rsds_25 no
spartan-3 fpga family: introduction and ordering information 4 www.xilinx.com ds099-1 (v1.2) december 24, 2003 1-800-255-7778 advance product specification 6 r product ordering and availability ta b l e 4 shows all valid device ordering combinations of device density, speed grade, package, and temperature range parameters for the spartan-3 family as well as the availability status of those combinations. table 3: spartan-3 i/o chart device available user i/os and differential (diff) i/o pairs vq100 tq144 pq208 ft256 fg320 fg456 fg676 fg900 fg1156 user diff user diff user diff user diff user diff user diff user diff user diff user diff xc3s506329974612456------------ xc3s200 63 29 97 46 141 62 173 76 - - - - - - - - - - xc3s400 - - 97 46 141 62 173 76 221 100 264 116 - - - - - - xc3s1000 - - - - - - 173 76 221 100 333 149 391 175 - - - - xc3s1500 - - - - - - - - 221 100 333 149 487 221 - - - - xc3s2000------------489221565270-- xc3s4000--------------633300712312 xc3s5000--------------633300784344 notes: 1. all device options listed in a given package column are pin-compatible. table 4: spartan-3 device availability package type (1) : vqfp tqfp pqfp ftbga fbga code: vq100 tq144 pq208 ft256 fg320 fg456 fg676 fg900 fg1156 device xc3s50 (c, i)(c, i)(c, i)------ xc3s200 (c, i) (c, i) (c, i) (c, i) - - - - - xc3s400 - (c, i) (c, i) (c, i) (c, i) (c, i) - - - xc3s1000 - - - (c, i) (c, i) (c, i) (c, i) - - xc3s1500 - - - - (c, i) (c, i) (c, i) - - xc3s2000 ------(c, i)(c, i)- xc3s4000 -------(c, i)(c, i) xc3s5000 -------(c, i)(c, i) notes: 1. package types are explained in ordering information , page 5 . 2. commercial devices are offered in the -4 and -5 speed grades; industrial devices are only in the -4 speed grade. 3. c = commercial, t j = 0 to +85 c; i = industrial, t j = ?40 c to +100 c. 4. parentheses indicate that a given device is not yet released to production. contact your local sales office for availability information.
spartan-3 fpga family: introduction and ordering information ds099-1 (v1.2) december 24, 2003 www.xilinx.com 5 advance product specification 1-800-255-7778 r ordering information package marking revision history the spartan-3 family data sheet ds099-1 , spartan-3 fpga family: introduction and ordering information (module 1) ds099-2 , spartan-3 fpga family: functional description (module 2) ds099-3 , spartan-3 fpga family: dc and switching characteristics (module 3) ds099-4 , spartan-3 fpga family: pinout descriptions (module 4) xc3s50 -4 pq208 c example: temperature range package type / number of pins device type speed grade device speed grade package type / number of pins temperature range (t j ) xc3s50 -4 standard performance vq100 100-pin very thin quad flat pack (vqfp) c commercial (0c to 85c) xc3s200 -5 high performance tq144 144-pin thin quad flat pack (tqfp) i industrial (?40c to 100c) xc3s400 pq208 208-pin plastic quad flat pack (pqfp) xc3s1000 ft256 256-ball fine-pitch thin ball grid array (ftbga) xc3s1500 fg320 320-ball fine-pitch ball grid array (fbga) xc3s2000 fg456 456-ball fine-pitch ball grid array (fbga) xc3s4000 fg676 676-ball fine-pitch ball grid array (fbga) xc3s5000 fg900 900-ball fine-pitch ball grid array (fbga) fg1156 1156-ball fine-pitch ball grid array (fbga) date version no. description 04/11/03 1.0 initial xilinx release. 04/24/03 1.1 updated block ram, dcm, and multiplier counts for the xc3s50. 12/24/03 1.2 added the fg320 package. lot code date code xc3s50 tm pq208xxx0350 xxxxxxxxx 4c spartan device type package speed grade operating range r r ds099-1_02_122403
spartan-3 fpga family: introduction and ordering information 6 www.xilinx.com ds099-1 (v1.2) december 24, 2003 1-800-255-7778 advance product specification 6 r
ds099-2 (v1.2) july 11, 2003 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2003 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. iobs iob overview the input/output block (iob) provides a programmable, bidirectional interface between an i/o pin and the fpga?s internal logic. a simplified diagram of the iob?s internal structure appears in figure 1 . there are three main signal paths within the iob: the output path, input path, and 3-state path. each path has its own pair of storage elements that can act as either registers or latches. for more information, see the storage element functions section. the three main signal paths are as follows: the input path carries data from the pad, which is bonded to a package pin, through an optional programmable delay element directly to the i line. after the delay element, there are alternate routes through a pair of storage elements to the iq1 and iq2 lines. the iob outputs i, iq1, and iq2 all lead to the fpga?s internal logic. the delay element can be set to ensure a hold time of zero. the output path, starting with the o1 and o2 lines, carries data from the fpga?s internal logic through a multiplexer and then a three-state driver to the iob pad. in addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. the 3-state path determines when the output driver is high impedance. the t1 and t2 lines carry data from the fpga?s internal logic through a multiplexer to the output driver. in addition to this direct path, the multiplexer provides the option to insert a pair of storage elements. all signal paths entering the iob, including those associated with the storage elements, have an inverter option. any inverter placed on these paths is automatically absorbed into the iob. storage element functions there are three pairs of storage elements in each iob, one pair for each of the three paths. it is possible to configure each of these storage elements as an edge-triggered d-type flip-flop (fd) or a level-sensitive latch (ld). the storage-element-pair on either the output path or the three-state path can be used together with a special multi- plexer to produce double-data-rate (ddr) transmission. this is accomplished by taking data synchronized to the clock signal?s rising edge and converting them to bits syn- chronized on both the rising and the falling edge. the com- bination of two registers and a multiplexer is referred to as a double-data-rate d-type flip-flop (fddr). see double-data-rate transmission , page 3 for more information. the signal paths associated with the storage element are described in ta b l e 1 . 040 spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 00 advance product specification r table 1: storage element signal description storage element signal description function d data input data at this input is stored on the active edge of ck enabled by ce. for latch operation when the input is enabled, data passes directly to the output q. q data output the data on this output reflects the state of the storage element. for operation as a latch in transparent mode, q will mirror the data at d. ck clock input a signal?s active edge on this input with ce asserted, loads data into the storage element. ce clock enable input when asserted, this input enables ck. if not connected, ce defaults to the asserted state. sr set/reset forces storage element into the state specified by the srhigh/srlow attributes. the sync/async attribute setting determines if the sr input is synchronized to the clock or not. rev reverse used together with sr. forces storage element into the state opposite from what sr does.
spartan-3 1.2v fpga family: functional description 2 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r figure 1: simplified iob diagram d ce ck tff1 three-state path t t1 tce t2 tff2 q sr ddr mux rev d ce ck q sr rev d ce ck off1 output path o1 oce o2 off2 q sr ddr mux weak keeper latch v cco v ref pin i/o pin from adjacent iob ds099_01_040703 i/o pin program- mable output driver dci esd weak pull-up weak pull- down esd rev d ce ck q sr rev otclk1 otclk2 d ce ck iff1 input path i ice iff2 q sr fixed delay lvcmos, lvttl, pci single-ended standards using v ref differential standards rev d ce ck q sr rev iclk1 iclk2 sr rev note: all iob signals communicating with the fpga's internal logic have the option of inverting polarity. iq1 iq2
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 3 advance product specification 1-800-255-7778 r according to figure 1 , the clock line otclk1 connects the ck inputs of the upper registers on the output and three-state paths. similarly, otclk2 connects the ck inputs for the lower registers on the output and three-state paths. the upper and lower registers on the input path have independent clock lines: iclk1 and iclk2. the enable line oce connects the ce inputs of the upper and lower registers on the output path. similarly, tce con- nects the ce inputs for the register pair on the three-state path and ice does the same for the register pair on the input path. the set/reset (sr) line entering the iob is common to all six registers, as is the reverse (rev) line. each storage element supports numerous options in addi- tion to the control over signal polarity described in the iob overview section. these are described in ta b l e 2 . double-data-rate transmission double-data-rate (ddr) transmission describes the tech- nique of synchronizing signals to both the rising and falling edges of the clock signal. spartan-3 devices use regis- ter-pairs in all three iob paths to perform ddr operations. the pair of storage elements on the iob?s output path (off1 and off2), used as registers, combine with a spe- cial multiplexer to form a ddr d-type flip-flop (fddr). this primitive permits ddr transmission where output data bits are synchronized to both the rising and falling edges of a clock. it is possible to access this function by placing either an fddrrse or an fddrcpe component or symbol into the design. ddr operation requires two clock signals (50% duty cycle), one the inverted form of the other. these sig- nals trigger the two registers in alternating fashion, as shown in figure 2 . commonly, the digital clock manager (dcm) generates the two clock signals by mirroring an incoming signal, then shifting it 180 degrees. this approach ensures minimal skew between the two signals. the storage-element-pair on the three-state path (tff1 and tff2) can also be combined with a local multiplexer to form an fddr primitive. this permits synchronizing the out- put enable to both the rising and falling edges of a clock. this ddr operation is realized in the same way as for the output path. the storage-element-pair on the input path (iff1 and iff2) allows an i/o to receive a ddr signal. an incoming ddr clock signal triggers one register and the inverted clock sig- nal triggers the other register. in this way, the registers take turns capturing bits of the incoming ddr data signal. aside from high bandwidth data transfers, ddr can also be used to reproduce, or ?mirror?, a clock signal on the output. this approach is used to transmit clock and data signals together. a similar approach is used to reproduce a clock signal at multiple outputs. the advantage for both approaches is that skew across the outputs will be minimal. table 2: storage element options option switch function specificity ff/latch chooses between an edge-sensitive flip-flop or a level-sensitive latch independent for each storage element. sync/async determines whether sr is synchronous or asynchronous independent for each storage element. srhigh/srlow determines whether sr acts as a set, which forces the storage element to a logic ?1" (srhigh) or a reset, which forces a logic ?0? (srlow). independent for each storage element, except when using fddr. in the latter case, the selection for the upper element (off1 or tff2) will apply to both elements. init1/init0 in the event of a global set/reset, after configuration or upon activation of the gts net, this switch decides whether to set or reset a storage element. by default, choosing srlow also selects init0; choosing srhigh also selects init1. independent for each storage element, except when using fddr. in the latter case, selecting init0 for one element applies to both elements (even though init1 is selected for the other).
spartan-3 1.2v fpga family: functional description 4 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r pull-up and pull-down resistors the optional pull-up and pull-down resistors are intended to establish high and low levels, respectively, at unused i/os. the weak pull-up resistor optionally connects each iob pad to v cco . a weak pull-down resistor optionally connects each pad to gnd. these resistors are placed in a design using the pullup and pulldown symbols in a sche- matic, respectively. they can also be instantiated as com- ponents, set as constraints or passed as attributes in hdl code. these resistors can also be selected for all unused i/o using the bitstream generator (bitgen) option unused- pin. a low logic level on hswap_en activates the pull-up resistors on all i/os during configuration. weak-keeper circuit each i/o has an optional weak-keeper circuit that retains the last logic level on a line after all drivers have been turned off. this is useful to keep bus lines from floating when all connected drivers are in a high-impedance state. this func- tion is placed in a design using the keeper symbol. pull-up and pull-down resistors override the weak-keeper circuit. esd protection clamp diodes protect all device pads against damage from electro-static discharge (esd) as well as excessive voltage transients. each i/o has two clamp diodes: one diode extends p-to-n from the pad to v cco and a second diode extends n-to-p from the pad to gnd. during operation, these diodes are normally biased in the off state. these clamp diodes are always connected to the pad, regardless of the signal standard selected. the presence of diodes lim- its the ability of spartan-3 i/os to tolerate high signal volt- ages. the v in absolute maximum rating in ta bl e 1 in module 3: dc and switching characteristics specifies the voltage range that i/os can tolerate. slew rate control and drive strength two options, fast and slow, control the output slew rate. the fast option supports output switching at a high rate. the slow option reduces bus transients. these options are only available when using one of the lvcmos or lvttl standards, which also provide up to seven different levels of current drive strength: 2, 4, 6, 8, 12, 16, and 24 ma. choos- ing the appropriate drive strength level is yet another means to minimize bus transients. ta b l e 3 shows the drive strengths that the lvcmos and lvttl standards support. the fast option is indicated by appending an "f" attribute after the output buffer symbol obuf or the bidirectional buffer symbol iobuf. the slow option appends an "s" attribute. the drive strength in milliam- peres follows the slew rate attribute. for example, obuf_lvcmos18_s_6 or iobuf_lvcmos25_f_16. boundary-scan capability all spartan-3 iobs support boundary-scan testing compat- ible with ieee 1149.1 standards. see boundary-scan (jtag) mode , page 36 for more information. selectio signal standards the iobs support 17 different single-ended signal stan- dards, as listed in ta b l e 4 . furthermore, the majority of iobs can be used in specific pairs supporting any of six dif- ferential signal standards, as shown in ta b l e 5 . the desired standard is selected by placing the appropriate i/o library symbol or component into the fpga design. for example, the symbol named iobuf_lvcmos15_f_8 represents a bidirectional i/o to which the 1.5v lvcmos signal standard has been assigned. the slew rate and current drive are set to fast and 8 ma, respectively. together with placing the appropriate i/o symbol, two exter- nally applied voltage levels, v cco and v ref select the desired signal standard. the v cco lines provide current to the output driver. the voltage on these lines determines the figure 2: clocking the ddr register d1 clk1 ddr mux dcm q1 fddr d2 clk2 q2 180? 0? ds099-2_02_070303 q ta b l e 3 : programmable output drive current signal standard current drive (ma) 2 4 6 8 12 16 24 lv c m o s 1 2 333 ---- lv c m o s 1 5 33333 -- lv c m o s 1 8 333333 - lv c m o s 2 5 3333333 lv c m o s 3 3 3333333 lvttl 3333333
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 5 advance product specification 1-800-255-7778 r output voltage swing for all standards except gtl and gtlp. all single-ended standards except the lvcmos modes require a reference voltage (v ref ) to bias the input-switch- ing threshold. once a configuration data file is loaded into the fpga that calls for the i/os of a given bank to use such a signal standard, a few specifically reserved i/o pins on the same bank automatically convert to v ref inputs. when using one of the lvcmos standards, these pins remain i/os because the v cco voltage biases the input-switching threshold, so there is no need for v ref . select the v cco and v ref levels to suit the desired single-ended standard according to ta b l e 4 . differential standards employ a pair of signals, one the opposite polarity of the other. the noise canceling (e.g., common-mode rejection) properties of these standards permit exceptionally high data transfer rates. this section introduces the differential signaling capabilities of spartan-3 devices. each device-package combination designates specific i/o pairs that are specially optimized to support differential standards. a unique ?l-number?, part of the pin name, iden- tifies the line-pairs associated with each bank (see module 4: pinout descriptions ). for each pair, the letters ?p? and ?n? designate the true and inverted lines, respectively. for example, the pin names io_l43p_7 and io_l43n_7 indi- cate the true and inverted lines comprising the line pair l43 on bank 7. the differential output voltage (v od ) parameter measures the voltage difference the high and low logic lev- els that a pair of differential outputs drive. the v od range for each of the differential standards is listed in ta b l e 5 . the v cco lines provide current to the outputs. the v ref lines are not used. select the v cco level to suit the desired differ- ential standard according to ta b l e 5 . the need to supply v ref and v cco imposes constraints on which standards can be used in the same bank. see the organization of iobs into banks section for additional guidelines concerning the use of the v cco and v ref lines. digitally controlled impedance (dci) when the round-trip delay of an output signal ? i.e., from output to input and back again ? exceeds rise and fall times, it is common practice to add termination resistors to the line carrying the signal. these resistors effectively match the impedance of a device?s i/o to the characteristic impedance of the transmission line, thereby preventing reflections that adversely affect signal integrity. however, with the high i/o counts supported by modern devices, add- ing resistors requires significantly more components and board area. furthermore, for some packages ? e.g., ball grid arrays ? it may not always be possible to place resis- tors close to pins. dci answers these concerns by providing two kinds of on-chip terminations: parallel terminations make use of an integrated resistor network. series terminations result from controlling the impedance of output drivers. dci actively adjusts both parallel and series terminations to accurately table 4: single-ended i/o standards (values in volts) signal standard v cco v ref for inputs (1) board termination voltage (v tt ) for outputs for inputs gtl note 2 note 2 0.8 1.2 gtlp note 2 note 2 1 1.5 hstl_i 1.5 - 0.75 0.75 hstl_iii 1.5 -0.9 1.5 hstl_i_18 1.8 -0.9 0.9 hstl_ii_18 1.8 -0.9 0.9 hstl_iii_18 1.8 -1.1 1.8 lv c mo s1 2 1. 2 1. 2 - - lv c mo s1 5 1. 5 1. 5 - - lv c mo s1 8 1. 8 1. 8 - - lv c mo s2 5 2. 5 2. 5 - - lv c mo s3 3 3. 3 3. 3 - - lv t tl 3. 3 3. 3 - - pci33_3 3.0 3.0 - - sstl18_i 1.8 -0.9 0.9 sstl2_i 2.5 - 1.25 1.25 sstl2_ii 2.5 - 1.25 1.25 notes: 1. banks 4 and 5 of any spartan-3 device in a vq100 package do not support signal standards using v ref . 2. the v cco level used for the gtl and gtlp standards must be no lower than the termination voltage (v tt ), nor can it be lower than the voltage at the i/o pad. 3. see ta b l e 6 for a listing of the single-ended dci standards. ta b l e 5 : differential i/o standards signal standard v cco (volts) v ref for inputs (volts) v od (1) (mv) for outputs for inputs min. max. ldt_25 2.5 - - 430 670 lv d s _2 5 2.5 - - 250 400 blvds_25 2.5 - - 250 450 lvdsext_25 2.5 - - 330 700 ulvds_25 2.5 - - 430 670 rsds_25 2.5 - - 100 400 notes: 1. measured with a termination resistor value (rt) of 100 ohms. 2. see ta b l e 6 for a listing of the differential dci standards. ta b l e 4 : single-ended i/o standards (values in volts) signal standard v cco v ref for inputs (1) board termination voltage (v tt ) for outputs for inputs
spartan-3 1.2v fpga family: functional description 6 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r match the characteristic impedance of the transmission line. this adjustment process compensates for differences in i/o impedance that can result from normal variation in the ambient temperature, the supply voltage and the manufac- turing process. when the output driver turns off, the series termination, by definition, approaches a very high imped- ance; in contrast, parallel termination resistors remain at the targeted values. dci is available only for certain i/o standards, as listed in ta b l e 6 . dci is selected by applying the appropriate i/o standard extensions to symbols or components. there are five basic ways to configure terminations, as shown in ta b l e 7 . the dci i/o standard determines which of these terminations is put into effect. table 6: dci i/o standards category of signal standard signal standard v cco (v) v ref for inputs (v) termination type for outputs for inputs at output at input single-ended gunning transceiver logic gtl_dci 1.2 1.2 0.8 single single gtlp_dci 1.5 1.5 1.0 high-speed transceiver logic hstl_i_dci 1.5 1.5 0.75 none split hstl_iii_dci 1.5 1.5 0.9 none single hstl_i_dci_18 1.8 1.8 0.9 none split hstl_ii_dci_18 1.8 1.8 0.9 split hstl_iii_dci_18 1.8 1.8 1.1 none single low-voltage cmos lvdci_15 1.5 1.5 - controlled impedance driver none lvdci_18 1.8 1.8 - lvdci_25 2.5 2.5 - lvdci_33 3.3 3.3 - lvdci_dv2_15 1.5 1.5 - controlled driver with half-impedance lvdci_dv2_18 1.8 1.8 - lvdci_dv2_25 2.5 2.5 - lvdci_dv2_33 3.3 3.3 - stub series terminated logic sstl18_i_dci 1.8 1.8 0.9 25-ohm driver split sstl2_i_dci 2.5 2.5 1.25 25-ohm driver sstl2_ii_dci 2.5 2.5 1.25 split with 25-ohm driver differential low-voltage differential signalling lvds_25_dci 2.5 2.5 - none split on each line of pair lvdsext_25_dci 2.5 2.5 - notes: 1. bank 5 of any spartan-3 device in a vq100 or tq144 package does not support dci signal standards.
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 7 advance product specification 1-800-255-7778 r table 7: dci terminations termination schematic (1) i/o standards controlled impedance output driver lvdci_15 lvdci_18 lvdci_25 lvdci_33 controlled output driver with half impedance lvdci_dv2_15 lvdci_dv2_18 lvdci_dv2_25 lvdci_dv2_33 single resistor gtl_dci gtlp_dci hstl_iii_dci (2) hstl_iii_dci_18 (2) split resistors hstl_i_dci (2) hstl_i_dci_18 (2) hstl_ii_dci_18 lvds_25_dci lvdsext_25_dci split resistors with output driver impedance fixed to 25 ? sstl18_i_dci (3) sstl2_i_dci (3) sstl2_ii_dci notes: 1. the value of r is equivalent to the characteristic impedance of the line connected to the i/o. it is also equal to half the v alue of r ref for the dv2 standards and r ref for all other dci standards. 2. for dci using hstl classes i and iii, terminations only go into effect at inputs (not at outputs). 3. for dci using sstl class i, the split termination only goes into effect at inputs (not at outputs). z 0 iob r z 0 iob r/2 r z 0 v cco iob 2r 2r z 0 v cco iob 25 ? 2r 2r z 0 v cco iob
spartan-3 1.2v fpga family: functional description 8 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r the dci feature operates independently for each of the device?s eight banks. each bank has an "n" reference pin (vrn) and a "p" reference pin, (vrp), to calibrate driver and termination resistance. only when using a dci stan- dard on a given bank do these two pins function as vrn and vrp. when not using a dci standard, the two pins func- tion as user i/os. as shown in figure 3 , add an external ref- erence resistor to pull the vrn pin up to v cco and another reference resistor to pull the vrp pin down to gnd. both resistors have the same value ? commonly 50 ohms ? with one-percent tolerance, which is either the characteristic impedance of the line or twice that, depending on the dci standard in use. standards having a symbol name that con- tains the letters ?dv2? use a reference resistor value that is twice the line impedance. dci adjusts the output driver impedance to match the reference resistors? value or half that, according to the standard. dci always adjusts the on-chip termination resistors to directly match the reference resistors? value. the rules guiding the use of dci standards on banks are as follows: 1. no more than one dci i/o standard with a single termination is allowed per bank. 2. no more than one dci i/o standard with a split termination is allowed per bank. 3. single termination, split termination, controlled- impedance driver, and controlled-impedance driver with half impedance can co-exist in the same bank. see also the organization of iobs into banks , page 8 . the organization of iobs into banks iobs are allocated among eight banks, so that each side of the device has two banks, as shown in figure 4 . for all packages, each bank has independent v ref lines. for example, v ref bank 3 lines are separate from the v ref lines going to all other banks. for the very thin quad flat pack (vq), plastic quad flat pack (pq), fine pitch thin ball grid array (ft), and fine pitch ball grid array (fg) packages, each bank has dedi- cated v cco lines. for example, the v cco bank 7 lines are separate from the v cco lines going to all other banks. thus, spartan-3 devices in these packages support eight inde- pendent v cco supplies. in contrast, the 144-pin thin quad flat pack (tq144) pack- age ties v cco together internally for the pair of banks on each side of the device. for example, the v cco bank 0 and the v cco bank 1 lines are tied together. the interconnected bank-pairs are 0/1, 2/3, 4/5, and 6/7. as a result, spartan-3 devices in the tq144 package support four independent v cco supplies. spartan-3 compatibility within the spartan-3 family, all devices are pin-compatible by package. when the need for future logic resources out- grows the capacity of the spartan-3 device in current use, a larger device in the same package can serve as a direct replacement. larger devices may add extra v ref and v cco lines to support a greater number of i/os. in the larger device, more pins can convert from user i/os to v ref lines. also, additional v cco lines are bonded out to pins that were ?not connected? in the smaller device. thus, it is important to plan for future upgrades at the time of the board?s initial design by laying out connections to the extra pins. the spartan-3 family is not pin-compatible with any previ- ous xilinx fpga family. rules concerning banks when assigning i/os to banks, it is important to follow the following v cco rules: 1. leave no v cco pins unconnected on the fpga. 2. set all v cco lines associated with the (interconnected) bank to the same voltage level. 3. the v cco levels used by all standards assigned to the i/os of the (interconnected) bank(s) must agree. the xilinx development software checks for this. tables 4 , 5 , and 6 describe how different standards use the v cco supply. figure 3: connection of reference resistors (r ref ) ds099-2_04_091602 v cco vrn vrp one of eight i/o banks r ref (1%) r ref (1%) figure 4: spartan-3 i/o banks (top view) ds099-2_03_060102 bank 0 bank 1 bank 5 bank 4 bank 7 bank 6 bank 2 bank 3
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 9 advance product specification 1-800-255-7778 r 4. if none of the standards assigned to the i/os of the (interconnected) bank(s) use v cco , tie all associated v cco lines to 2.5v. 5. in general, apply 2.5v to v cco bank 4 from power-on to the end of configuration. apply the same voltage to v cco bank 5 during parallel configuration or a readback operation. for information on how to program the fpga using 3.3v signals and power, see the 3.3v-tolerant configuration interface section. if any of the standards assigned to the inputs of the bank use v ref , then observe the following additional rules: 1. leave no v ref pins unconnected on any bank. 2. set all v ref lines associated with the bank to the same voltage level. 3. the v ref levels used by all standards assigned to the inputs of the bank must agree. the xilinx development software checks for this. tables 4 and 6 describe how different standards use the v ref supply. if none of the standards assigned to the inputs of a bank use v ref for biasing input switching thresholds, all associ- ated v ref pins function as user i/os. exceptions to banks supporting i/o standards bank 5 of any spartan-3 device in a vq100 or tq144 pack- age does not support dci signal standards. in this case, bank 5 has neither vrn nor vrp pins. furthermore, banks 4 and 5 of any spartan-3 device in a vq100 package do not support signal standards using v ref (see ta bl e 4 ). in this case, the two banks do not have any v ref pins. supply voltages for the iobs three different supplies power the iobs: 1. the v cco supplies, one for each of the fpga?s i/o banks, power the output drivers, except when using the gtl and gtlp signal standards. the voltage on the v cco pins determines the voltage swing of the output signal. 2. v ccint is the main power supply for the fpga?s internal logic. 3. the v ccaux is an auxiliary source of power, primarily to optimize the performance of various fpga functions such as i/o switching. the i/os during power-on , configuration, and user mode with no power applied to the fpga, all i/os are in a high-impedance state. the v ccint (1.2v), v ccaux (2.5v), and v cco supplies may be applied in any order. before power-on can finish, v ccint , v cco bank 4, and v ccaux must have reached their respective minimum recom- mended operating levels (see ta bl e 2 in module 3: dc and switching characteristics ). at this time, all i/o drivers also will be in a high-impedance state. v cco bank 4, v ccint , and v ccaux serve as inputs to the internal power-on reset circuit (por). a low level applied to hswap_en input enables weak pull-up resistors on user i/os from power-on throughout configuration. a high level on hswap_en disables the pull-up resistors, allowing the i/os to float. as soon as power is applied, the fpga begins initializing its configura- tion memory. at the same time, the fpga internally asserts the global set-reset (gsr), which asynchronously resets all iob storage elements to a low state. upon the completion of initialization, init_b goes high, sampling the m0, m1, and m2 inputs to determine the con- figuration mode. at this point, the configuration data is loaded into the fpga. the i/o drivers remain in a high-impedance state (with or without pull-up resistors, as determined by the hswap_en input) throughout configura- tion. the global three state (gts) net is released during start-up, marking the end of configuration and the begin- ning of design operation in the user mode. at this point, those i/os to which signals have been assigned go active while all unused i/os remain in a high-impedance state. the release of the gsr net, also part of start-up, leaves the iob registers in a low state by default, unless the loaded design reverses the polarity of their respective rs inputs. in user mode, all weak, internal pull-up resistors on the i/os are disabled and hswap_en becomes a ?don?t care? input. if it is desirable to have weak pull-up or pull-down resistors on i/os carrying signals, the appropriate symbol ? e.g., pullup, pulldown ? must be placed at the appropriate pads in the design. the bitstream generator (bitgen) option unusedpin available in the xilinx development software determines whether unused i/os collectively have pull-up resistors, pull-down resistors, or no resistors in user mode.
spartan-3 1.2v fpga family: functional description 10 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r . clb overview the configurable logic blocks (clbs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. each clb comprises four intercon- nected slices, as shown in figure 5 . these slices are grouped in pairs. each pair is organized as a column with an independent carry chain. the nomenclature that the fpga editor ? part of the xilinx development software ? uses to designate slices is as fol- lows: the letter "x" followed by a number identifies columns of slices. the "x" number counts up in sequence from the left side of the die to the right. the letter "y" followed by a number identifies the position of each slice in a pair as well as indicating the clb row. the "y" number counts slices starting from the bottom of the die according to the sequence: 0, 1, 0, 1 (the first clb row); 2, 3, 2, 3 (the sec- ond clb row); etc. figure 5 shows the clb located in the lower left-hand corner of the die. slices x0y0 and x0y1 make up the column-pair on the left where as slices x1y0 and x1y1 make up the column-pair on the right. for each clb, the term ?left-hand? (or slicem) is used to indicated the pair of slices labeled with an even "x" number, such as x0, and the term ?right-hand? (or slicel) designates the pair of slices with an odd "x" number, e.g., x1. elements within a slice all four slices have the following elements in common: two logic function generators, two storage elements, wide-func- tion multiplexers, carry logic, and arithmetic gates, as shown in figure 6 . both the left-hand and right-hand slice pairs use these elements to provide logic, arithmetic, and rom functions. besides these, the left-hand pair supports two additional functions: storing data using distributed ram and shifting data with 16-bit registers. figure 6 is a diagram of the left-hand slice; therefore, it represents a superset of the elements and connections to be found in all slices. see function generator , page 12 for more information. the ram-based function generator ? also known as a look-up table or lut ? is the main resource for imple- menting logic functions. furthermore, the luts in each left-hand slice pair can be configured as distributed ram or a 16-bit shift register. for information on the former, see xapp464 : using look-up tables as distributed ram in spartan-3 fpgas ; for information on the latter, refer to xapp465 : using look-up tables as shift registers (srl16) in spartan-3 fpgas . the function generators located in the upper and lower portions of the slice are referred to as the "g" and "f", respectively. the storage element, which is programmable as either a d-type flip-flop or a level-sensitive latch, provides a means for synchronizing data to a clock signal, among other uses. the storage elements in the upper and lower portions of the slice are called ffy and ffx, respectively. wide-function multiplexers effectively combine luts in order to permit more complex logic operations. each slice has two of these multiplexers with f5mux in the lower por- tion of the slice and fxmux in the upper portion. depend- ing on the slice, fxmux takes on the name f6mux, f7mux, or f8mux. for more details on the multiplexers, see xapp466 : using dedicated multiplexers in spartan-3 fpgas . figure 5: arrangement of slices within the clb ds099-2_05_040703 interconnect to neighbors left-hand slicem (logic or distributed ram or shift register) right-hand slicel (logic only) cin slice x0y1 slice x0y0 switch matrix cout clb cout shiftout shiftin cin slice x1y1 slice x1y0
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 11 advance product specification 1-800-255-7778 r figure 6: simplified diagram of the left-hand slicem notes: 1. options to invert signal polarity as well as other options that enable lines for various functions are not shown. 2. the index i can be 6, 7, or 8, depending on the slice. in this position, the upper right-hand slice has an f8mux, and the upper left-hand slice has an f7mux. the lower right-hand and left-hand slices both have an f6mux.
spartan-3 1.2v fpga family: functional description 12 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r the carry chain, together with various dedicated arithmetic logic gates, support fast and efficient implementations of math operations. the carry chain enters the slice as cin and exits as cout. five multiplexers control the chain: cyinit, cy0f, and cymuxf in the lower portion as well as cy0g and cymuxg in the upper portion. the dedicated arithmetic logic includes the exclusive-or gates xorf and xorg (upper and lower portions of the slice, respectively) as well as the and gates gand and fand (upper and lower portions, respectively). main logic paths central to the operation of each slice are two nearly identi- cal data paths, distinguished using the terms top and bot- tom . the description that follows uses names associated with the bottom path. (the top path names appear in paren- theses.) the basic path originates at an interconnect-switch matrix outside the clb. four lines, f1 through f4 (or g1 through g4 on the upper path), enter the slice and connect directly to the lut. once inside the slice, the lower 4-bit path passes through a function generator "f" (or "g") that performs logic operations. the function generator?s data output, "d", offers five possible paths: 1. exit the slice via line "x" (or "y") and return to interconnect. 2. inside the slice, "x" (or "y") serves as an input to the dxmux (dymux) which feeds the data input, "d", of the ffy (ffx) storage element. the "q" output of the storage element drives the line xq (or yq) which exits the slice. 3. control the cymuxf (or cymuxg) multiplexer on the carry chain. 4. with the carry chain, serve as an input to the xorf (or xorg) exclusive-or gate that performs arithmetic operations, producing a result on "x" (or "y"). 5. drive the multiplexer f5mux to implement logic functions wider than four bits. the "d" outputs of both the f-lut and g-lut serve as data inputs to this multiplexer. in addition to the main logic paths described above, there are two bypass paths that enter the slice as bx and by. once inside the fpga, bx in the bottom half of the slice (or by in the top half) can take any of several possible branches: 1. bypass both the lut and the storage element, then exit the slice as bxout (or byout) and return to interconnect. 2. bypass the lut, then pass through a storage element via the d input before exiting as xq (or yq). 3. control the wide function multiplexer f5mux (or f6mux). 4. via multiplexers, serve as an input to the carry chain. 5. drives the di input of the lut. see distributed ram section. 6. by can control the rev inputs of both the ffy and ffx storage elements. see storage element section. 7. finally, the dig_mux multiplexer can switch by onto to the dig line, which exits the slice. other slice signals shown in figure 6, page 11 are dis- cussed in the sections that follow. function generator each of the two luts (f and g) in a slice have four logic inputs (a1-a4) and a single output (d). this permits any four-variable boolean logic operation to be programmed into them. furthermore, wide function multiplexers can be used to effectively combine luts within the same clb or across different clbs, making logic functions with still more input variables possible. the luts in both the right-hand and left-hand slice-pairs not only support the logic functions described above, but also can function as rom that is initialized with data at the time of configuration. the luts in the left-hand slice-pair (even-numbered col- umns such as x0 in figure 5 ) of each clb support two additional functions that the right-hand slice-pair (odd-num- bered columns such as x1) do not. first, it is possible to program the ?left-hand luts? as dis- tributed ram. this type of memory affords moderate amounts of data buffering anywhere along a data path. one left-hand lut stores 16 bits. multiple left-hand luts can be combined in various ways to store larger amounts of data. a dual port option combines two luts so that memory access is possible from two independent data lines. a distributed rom option permits pre-loading the memory with data dur- ing fpga configuration for more information, see the dis- tributed ram section. second, it is possible to program each left-hand lut as a 16-bit shift register. used in this way, each lut can delay serial data anywhere from one to 16 clock cycles. the four left-hand luts of a single clb can be combined to produce delays up to 64 clock cycles. the shiftin and shiftout lines cascade luts to form larger shift registers. it is also possible to combine shift registers across more than one clb. the resulting programmable delays can be used to balance the timing of data pipelines. block ram overview all spartan-3 devices support block ram, which is orga- nized as configurable, synchronous 18kbit blocks. block ram stores relatively large amounts of data more efficiently than the distributed ram feature described earlier. (the lat- ter is better suited for buffering small amounts of data any- where along signal paths.) this section describes basic block ram functions. for more information, see xapp463 : using block ram in spartan-3 fpgas .
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 13 advance product specification 1-800-255-7778 r the aspect ratio ? i.e., width vs. depth ? of each block ram is configurable. furthermore, multiple blocks can be cascaded to create still wider and/or deeper memories. a choice among primitives determines whether the block ram functions as dual- or single-port memory. a name of the form ram16_s[w a ]_s[w b ] calls out the dual-port primi- tive, where the integers w a and w b specify the total data path width at ports w a and w b , respectively. thus, a ram16_s9_s18 is a dual-port ram with a 9-bit-wide port a and an 18-bit-wide port b. a name of the form ram16_s[w] identifies the single-port primitive, where the integer w specifies the total data path width of the lone port. a ram16_s18 is a single-port ram with an 18-bit-wide port. other memory functions ? e.g., fifos, data path width conversion, rom, etc. ? are readily available using the core generator? system, part of the xilinx development software. arrangement of ram blocks on die the xc3s50 has one column of block ram. the spartan-3 devices ranging from the xc3s200 to xc3s2000 have two columns of block ram. the xc3s4000 and xc3s5000 have four columns. the position of the columns on the die is shown in figure 1 in module 1: introduction and ordering information . for a given device, the total available ram blocks are distributed equally among the columns. ta b l e 8 shows the number of ram blocks, the data storage capac- ity, and the number of columns for each device. the internal structure of the block ram the block ram has a dual port structure. the two identical data ports called a and b permit independent access to the common ram block, which has a maximum capacity of 18,432 bits ? or 16,384 bits when no parity lines are used. each port has its own dedicated set of data, control and clock lines for synchronous read and write operations. there are four basic data paths, as shown in figure 7 : (1) write to and read from port a, (2) write to and read from port b, (3) data transfer from port a to port b, and (4) data trans- fer from port b to port a. block ram port signal definitions representations of the dual-port primitive ram16_s[w a ]_s[w b ] and the single-port primitive ram16_s[w] with their associated signals are shown in figure 8a and figure 8b , respectively. these signals are defined in ta b l e 9 . table 8: number of ram blocks by device device total number of ram blocks total addressable locations (bits) number of columns xc3s50 4 73,728 1 xc3s200 12 221,184 2 xc3s400 16 294,912 2 xc3s1000 24 442,368 2 xc3s1500 32 589,824 2 xc3s2000 40 737,280 2 xc3s4000 96 1,769,472 4 xc3s5000 104 1,916,928 4 figure 7: block ram data paths ds099-2_12_030703 spartan-3 dual port block ram read 3 read write write read write write read port a port b 2 1 4
spartan-3 1.2v fpga family: functional description 14 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r figure 8: block ram primitives ds099-2_13_091302 wea ena ssra clka addra[r a 1:0] dia[w a 1:0] dipa[3:0] dopa[p a 1:0] doa[w a 1:0] ram16_w a _w b (a) dual-port (b) single-port dopb[p b 1:0] dob[w b 1:0] web enb ssrb clkb addrb[r b 1:0] dib[w b 1:0] dipb[3:0] we en ssr clk addr[r1:0] di[w1:0] dip[p1:0] dop[p1:0] do[w1:0] ram16_sw notes: 1. w a and w b are integers representing the total data path width (i.e., data bits plus parity bits) at ports a and b, respectively. 2. p a and p b are integers that indicate the number of data path lines serving as parity bits. 3. r a and r b are integers representing the address bus width at ports a and b, respectively. 4. the control signals clk, we, en, and ssr on both ports have the option of inverted polarity. table 9: block ram port signals signal description port a signal name port b signal name direction function address bus addra addrb input the address bus selects a memory location for read or write operations. the width (w) of the port?s associated data path determines the number of available address lines (r). data input bus dia dib input data at the di input bus is written to the addressed memory location addressed on an enabled active clk edge. it is possible to configure a port?s total data path width (w) to be 1, 2, 4, 9, 18, or 36 bits. this selection applies to both the di and do paths of a given port. each port is independent. for a port assigned a width (w), the number of addressable locations will be 16,384/(w-p) where "p" is the number of parity bits. each memory location will have a width of "w" (including parity bits). see the dip signal description for more information of parity. parity data input(s) dipa dipb input parity inputs represent additional bits included in the data input path to support error detection. the number of parity bits "p" included in the di (same as for the do bus) depends on a port?s total data path width (w). see ta bl e 1 0 .
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 15 advance product specification 1-800-255-7778 r port aspect ratios on a given port, it is possible to select a number of different possible widths (w ? p) for the di/do buses as shown in ta b l e 1 0 . these two buses always have the same width. this data bus width selection is independent for each port. if the data bus width of port a differs from that of port b, the block ram automatically performs a bus-matching function. when data are written to a port with a narrow bus, then read from a port with a wide bus, the latter port will effectively combine ?narrow? words to form ?wide? words. similarly, when data are written into a port with a wide bus, then read from a port with a narrow bus, the latter port will divide data output bus doa dob output basic data access occurs whenever we is inactive. the do outputs mirror the data stored in the addressed memory location. data access with we asserted is also possible if one of the following two attributes is chosen: write_first accesses data before the write takes place. read_first accesses data after the write occurs. a third attribute, no_change, latches the do outputs upon the assertion of we. it is possible to configure a port?s total data path width (w) to be 1, 2, 4, 9, 18, or 36 bits. this selection applies to both the di and do paths. see the di signal description. parity data output(s) dopa dopb output parity inputs represent additional bits included in the data input path to support error detection. the number of parity bits "p" included in the di (same as for the do bus) depends on a port?s total data path width (w). see ta bl e 1 0 . write enable wea web input when asserted together with en, this input enables the writing of data to the ram. in this case, the data access attributes write_first, read_first or no_change determines if and how data is updated on the do outputs. see the do signal description. when we is inactive with en asserted, read operations are still possible. in this case, a transparent latch passes data from the addressed memory location to the do outputs. clock enable ena enb input when asserted, this input enables the clk signal to synchronize block ram functions as follows: the writing of data to the di inputs (when we is also asserted), the updating of data at the do outputs as well as the setting/resetting of the do output latches. when de-asserted, the above functions are disabled. set/reset ssra ssrb input when asserted, this pin forces the do output latch to the value that the srval attribute is set to. a set/reset operation on one port has no effect on the other ports functioning, nor does it disturb the memory?s data contents. it is synchronized to the clk signal. clock clka clkb input this input accepts the clock signal to which read and write operations are synchronized. all associated port inputs are required to meet setup times with respect to the clock signal?s active edge. the data output bus responds after a clock-to-out delay referenced to the clock signal?s active edge. table 9: block ram port signals (continued) signal description port a signal name port b signal name direction function
spartan-3 1.2v fpga family: functional description 16 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r ?wide? words to form ?narrow? words. when the data bus width is eight bits or greater, extra parity bits become avail- able. the width of the total data path (w) is the sum of the di/do bus width and any parity bits (p). the width selection made for the di/do bus determines the number of address lines according to the relationship expressed below: r = 14 ? [log(w?p)/log(2)] (1) in turn, the number of address lines delimits the total num- ber (n) of addressable locations or depth according to the following equation: n = 2 r (2) the product of w and n yields the total block ram capacity. equations (1) and (2) show that as the data bus width increases, the number of address lines along with the num- ber of addressable memory locations decreases. using the permissible di/do bus widths as inputs to these equations provides the bus width and memory capacity measures shown in ta bl e 1 0 . block ram data operations writing data to and accessing data from the block ram are synchronous operations that take place independently on each of the two ports. the waveforms for the write operation are shown in the top half of the figure 9 , figure 10 , and figure 11 . when the we and en signals enable the active edge of clk, data at the di input bus is written to the block ram location addressed by the addr lines. there are a number of different conditions under which data can be accessed at the do outputs. basic data access always occurs when the we input is inactive. under this condition, data stored in the memory location addressed by the addr lines passes through a transparent output latch to the do outputs. the timing for basic data access is shown in the portions of figure 9 , figure 10 , and figure 11 during which we is low. data can also be accessed on the do outputs when assert- ing the we input. this is accomplished using two different attributes: choosing the write_first attribute, data is written to the addressed memory location on an enabled active clk edge and is also passed to the do outputs. write_first timing is shown in the portion of figure 9 during which we is high. table 10: port aspect ratios for port a or b di/do bus width (w ? p bits) dip/dop bus width (p bits) total data path width (w bits) addr bus width (r bits) no. of addressable locations (n) block ram capacity (bits) 1 0 1 14 16,384 16,384 2 0 2 13 8,192 16,384 4 0 4 12 4,096 16,384 8 1 9 11 2,048 18,432 16 2 18 10 1,024 18,432 32 4 36 9 512 18,432
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 17 advance product specification 1-800-255-7778 r choosing the read_first attribute, data already stored in the addressed location pass to the do outputs before that location is over-written with new data from the di inputs on an enabled active clk edge. read_first timing is shown in the portion of figure 10 during which we is high. choosing a third attribute called no_change puts the do outputs in a latched state when asserting we. under this condition, the do outputs will retain the data driven just before we was asserted. no_change timing is shown in the portion of figure 11 during which we is high. figure 9: waveforms of block ram data operations with write_first selected clk we di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) 1111 2222 mem(dd) read write mem(bb)=1111 write mem(cc)=2222 ds099-2_14_030403 figure 10: waveforms of block ram data operations with read_first selected clk we di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) old mem(bb) old mem(cc) mem(dd) read write mem(bb)=1111 write mem(cc)=2222 ds099-2_15_030403
spartan-3 1.2v fpga family: functional description 18 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r dedicated multipliers all spartan-3 devices provide embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit prod- uct. this section provides an introduction to multipliers. for further details, see xapp467 : using embedded multipliers in spartan-3 fpgas . the input buses to the multiplier accept data in two?s-com- plement form (either 18-bit signed or 17-bit unsigned). one such multiplier is matched to each block ram on the die. the close physical proximity of the two ensures efficient data handling. cascading multipliers permits multiplicands more than three in number as well as wider than 18-bits. the multiplier is placed in a design using one of two primi- tives: an asynchronous version called mult18x18 and a version with a register at the outputs called mult18x18s, as shown in figure 12a and figure 12b , respectively. the signals for these primitives are defined in ta b l e 1 1 . the core generator system produces multipliers based on these primitives that can be configured to suit a wide range of requirements. figure 11: waveforms of block ram data op erations with no_change selected clk we di addr do en disabled read xxxx 1111 2222 xxxx aa bb cc dd 0000 mem(aa) mem(dd) read write mem(bb)=1111 write mem(cc)=2222 ds099-2_16_030403 figure 12: embedded multiplier primitives ds099-2_17_091302 (a) asynchronous 18-bit multiplier (b) 18-bit multiplier with register at outputs a[17:0] b[17:0] p[35:0] mult18x18 a[17:0] b[17:0] clk ce rst p[35:0] mult18x18s
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 19 advance product specification 1-800-255-7778 r digital clock manager (dcm) spartan-3 devices provide flexible, complete control over clock frequency, phase shift and skew through the use of the dcm feature. to accomplish this, the dcm employs a delay-locked loop (dll), a fully digital control system that uses feedback to maintain clock signal characteristics with a high degree of precision despite normal variations in oper- ating temperature and voltage. this section provides a fun- damental description of the dcm. for further information, see xapp462 : using digital clock managers (dcms) in spartan-3 fpgas . each member of the spartan-3 family has four dcms, except the smallest, the xc3s50, which has two dcms. the dcms are located at the ends of the outermost block ram column(s). see figure 1 in module 1: introduction and ordering information . the digital clock manager is placed in a design as the ?dcm? primitive. the dcm supports three major functions: clock-skew elimination: clock skew describes the extent to which clock signals may, under normal circumstances, deviate from zero-phase alignment. it occurs when slight differences in path delays cause the clock signal to arrive at different points on the die at different times. this clock skew can increase set-up and hold time requirements as well as clock-to-out time, which may be undesirable in applications operating at a high frequency, when timing is critical. the dcm eliminates clock skew by aligning the output clock signal it generates with another version of the clock signal that is fed back. as a result, the two clock signals establish a zero-phase relationship. this effectively cancels out clock distribution delays that may lie in the signal path leading from the clock output of the dcm to its feedback input. frequency synthesis: provided with an input clock signal, the dcm can generate a wide range of different output clock frequencies. this is accomplished by either multiplying and/or dividing the frequency of the input clock signal by any of several different factors. phase shifting: the dcm provides the ability to shift the phase of all its output clock signals with respect to its input clock signal. table 11: embedded multiplier primitives descriptions signal name direction function a[17:0] input apply one 18-bit multiplicand to these inputs. the mult18x18s primitive requires a setup time before the enabled rising edge of clk. b[17:0] input apply the other 18-bit multiplicand to these inputs. the mult18x18s primitive requires a setup time before the enabled rising edge of clk. p[35:0] output the output on the p bus is a 36-bit product of the multiplicands a and b. in the case of the mult18x18s primitive, an enabled rising clk edge updates the p bus. clk input clk is only an input to the mult18x18s primitive. the clock signal applied to this input when enabled by ce, updates the output register that drives the p bus. ce input ce is only an input to the mult18x18s primitive. enable for the clk signal. asserting this input enables the clk signal to update the p bus. rst input rst is only an input to the mult18x18s primitive. asserting this input resets the output register on an enabled, rising clk edge, forcing the p bus to all zeroes. notes: 1. the control signals clk, ce and rst have the option of inverted polarity.
spartan-3 1.2v fpga family: functional description 20 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r the dcm has four functional components: the delay-locked loop (dll), the digital frequency synthe- sizer (dfs), the phase shifter (ps), and the status logic. each component has its associated signals, as shown in figure 13 . delay-locked loop (dll) the most basic function of the dll component is to elimi- nate clock skew. the main signal path of the dll consists of an input stage, followed by a series of discrete delay ele- ments or taps, which in turn leads to an output stage. this path together with logic for phase detection and control forms a system complete with feedback as shown in figure 14 . figure 13: dcm functional blocks and associated signals ds099-2_07_040103 psincdec psen psclk clkin clkfb rst status [7:0] locked 8 clkfx180 clkfx clk0 psdone clock distribution delay clk90 clk180 clk270 clk2x clk2x180 clkdv status logic dfs dll phase shifter delay taps output stage input stage dcm figure 14: simplified functional diagram of dll ds099-2_08_041103 clkin delay n clkfb rst clk0 clk90 clk180 clk270 clk2x clk2x180 clkdv output section control delay n-1 phase detection locked delay 2 delay 1
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 21 advance product specification 1-800-255-7778 r the dll component has two clock inputs, clkin and clkfb, as well as seven clock outputs, clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv as described in ta b l e 1 2 . the clock outputs drive simulta- neously; however, the high frequency mode only supports a subset of the outputs available in the low frequency mode. see dll frequency modes , page 23 . signals that initialize and report the state of the dll are discussed in the status logic component , page 28 . the clock signal supplied to the clkin input serves as a reference waveform, with which the dll seeks to align the feedback signal at the clkfb input. when eliminating clock skew, the common approach to using the dll is as follows: the clk0 signal is passed through the clock distribution network to all the registers it synchronizes. these registers are either internal or external to the fpga. after passing through the clock distribution network, the clock signal returns to the dll via a feedback line called clkfb. the control block inside the dll measures the phase error between clkfb and clkin. this phase error is a measure of the clock skew that the clock distribution network intro- duces. the control block activates the appropriate number of delay elements to cancel out the clock skew. once the dll has brought the clk0 signal in phase with the clkin signal, it asserts the locked output, indicating a ?lock? on to the clkin signal. dll attributes and related functions a number of different functional options can be set for the dll component through the use of the attributes described in ta b l e 1 3 . each attribute is described in detail in the sec- tions that follow: table 12: dll signals signal direction description mode support low frequency high frequency clkin input accepts original clock signal. yes yes clkfb input accepts either clk0 or clk2x as feed back signal. (set clk_feedback attribute accordingly). ye s ye s clk0 output generates clock signal with same frequency and phase as clkin. yes yes clk90 output generates clock signal with same frequency as clkin, only phase-shifted 90. ye s n o clk180 output generates clock signal with same frequency as clkin, only phase-shifted 180. ye s ye s clk270 output generates clock signal with same frequency as clkin, only phase-shifted 270. ye s n o clk2x output generates clock signal with same phase as clkin, only twice the frequency. ye s n o clk2x180 output generates clock signal with twice the frequency of clkin, phase-shifted 180 with respect to clkin. ye s n o clkdv output divides the clkin frequency by clkdv_divide value to generate lower frequency clock signal that is phase-aligned to clkin. ye s ye s
spartan-3 1.2v fpga family: functional description 22 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r dll clock input connections an external clock source enters the fpga using a global clock input buffer (ibufg), which directly accesses the glo- bal clock network or an input buffer (ibuf). clock signals within the fpga drive a global clock net using a global clock multiplexer buffer (bufgmux). the global clock net connects directly to the clkin input. the internal and exter- nal connections are shown in figure 15a and figure 15c , respectively. a differential clock (e.g., lvds) can serve as an input to clkin. dll clock output and feedback connections as many as four of the nine dcm clock outputs can simulta- neously drive the four bufgmux buffers on the same die edge (top or bottom). all dcm clock outputs can simulta- neously drive general routing resources, including intercon- nect leading to obuf buffers. the feedback loop is essential for dll operation and is established by driving the clkfb input with either the clk0 or the clk2x signal so that any undesirable clock distribu- tion delay is included in the loop. it is possible to use either of these two signals for synchronizing any of the seven dll outputs: clk0, clk90, clk180, clk270, clkdv, clk2x, or clk2x180. the value assigned to the clk_feedback attribute must agree with the physical feedback connection: a value of 1x for the clk0 case, 2x for the clk2x case. if the dcm is used in an application that does not require the dll ? i.e., only the dfs is used ? then there is no feed- back loop so clk_feedback is set to none. there are two basic cases that determine how to connect the dll clock outputs and feedback connections: on-chip synchronization and off-chip synchronization, which are illustrated in figure 15a through figure 15d . table 13: dll attributes attribute description values clk_feedback chooses either the clk0 or clk2x output to drive the clkfb input none, 1x, 2x dll_frequency_mode chooses between high frequency and low frequency modes low, high clkin_divide_by_2 halves the frequency of the clkin signal just as it enters the dcm true, false clkdv_divide selects constant used to divide the clkin input frequency to generate the clkdv output frequency 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16. duty_cycle_correction enables 50% duty cycle correction for the clk0, clk90, clk180, and clk270 outputs true, false
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 23 advance product specification 1-800-255-7778 r in the on-chip synchronization case ( figure 15a and figure 15b ), it is possible to connect any of the dll?s seven output clock signals through general routing resources to the fpga?s internal registers. either a global clock buffer (bufg) or a bufgmux affords access to the global clock network. as shown in figure 15a , the feedback loop is cre- ated by routing clk0 (or clk2x, in figure 15b ) to a global clock net, which in turn drives the clkfb input. in the off-chip synchronization case ( figure 15c and figure 15d ), clk0 (or clk2x) plus any of the dll?s other output clock signals exit the fpga using output buffers (obuf) to drive an external clock network plus registers on the board. as shown in figure 15c , the feedback loop is formed by feeding clk0 (or clk2x, in figure 15d ) back into the fpga using an ibufg, which directly accesses the global clock network, or an ibuf. then, the global clock net is connected directly to the clkfb input. dll frequency modes the dll supports two distinct operating modes, high fre- quency and low frequency, with each specified over a differ- ent clock frequency range. the dll_frequency_mode attribute chooses between the two modes. when the attribute is set to low, the low frequency mode permits all seven dll clock outputs to operate over a low-to-moderate frequency range. when the attribute is set to high, the high frequency mode allows the clk0, clk180 and clkdv out- puts to operate at the highest possible frequencies. the remaining dll clock outputs are not available for use in high frequency mode. accommodating high input frequencies if the frequency of the clkin signal is high such that it exceeds the maximum permitted, divide it down to an acceptable value using the clkin_divide_by_2 attribute. when this attribute is set to true, the clkin frequency is divided by a factor of two just as it enters the dcm. coarse phase shift outputs of the dll compo- nent in addition to clk0 for zero-phase alignment to the clkin signal, the dll also provides the clk90, clk180 and clk270 outputs for 90, 180 and 270 phase-shifted sig- nals, respectively. these signals are described in ta bl e 1 2 . figure 15: input clock, output clock, and feedback connections for the dll ds099-2_09_071003 clk90 clk180 clk270 clkdv clk2x clk2x180 clk0 clk0 clock net delay bufgmux bufgmux bufg fpga (a) on-chip with clk0 feedback clkin dcm clkfb clk90 clk180 clk270 clkdv clk2x clk2x180 clk0 clk0 clock net delay ibufg ibufg fpga (c) off-chip with clk0 feedback clkin dcm clkfb obufg obufg clk2x clk2x ibufg ibufg fpga (d) off-chip with clk2x feedback clkin dcm clkfb obufg obufg clk0 clk90 clk180 clk270 clkdv clk2x180 clk2x clk2x clock net delay clock net delay bufgmux bufgmux bufg fpga (b) on-chip with clk2x feedback clkin dcm clkfb clk0 clk90 clk180 clk270 clkdv clk2x180 notes: 1. in the low frequency mode, all seven dll outputs are available. in the high frequency mode, only the clk0, clk180, and clkdv outputs are available.
spartan-3 1.2v fpga family: functional description 24 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r their relative timing in the low frequency mode is shown in figure 16 . the clk90, clk180 and clk270 outputs are not available when operating in the high frequency mode. (see the description of the dll_frequency_mode attribute in ta b l e 1 3 .) for control in finer increments than 90, see the phase shifter (ps) , page 26 section. basic frequency synthesis outputs of the dll component the dll component provides basic options for frequency multiplication and division in addition to the more flexible synthesis capability of the dfs component, described in a later section. these operations result in output clock signals with frequencies that are either a fraction (for division) or a multiple (for multiplication) of the incoming clock frequency. the clk2x output produces an in-phase signal that is twice the frequency of clkin. the clk2x180 output also dou- bles the frequency, but is 180 out-of-phase with respect to clkin. the clkdiv output generates a clock frequency that is a predetermined fraction of the clkin frequency. the clkdv_divide attribute determines the factor used to divide the clkin frequency. the attribute can be set to var- ious values as described in ta b l e 1 3 . the basic frequency synthesis outputs are described in ta b l e 1 2 . their relative timing in the low frequency mode is shown in figure 16 . the clk2x and clk2x180 outputs are not available when operating in the high frequency mode. (see the description of the dll_frequency_mode attribute in ta bl e 1 4 .) duty cycle correction of dll clock outputs the clk2x (1) , clk2x180, and clkdv (2) output signals ordinarily exhibit a 50% duty cycle ? even if the incoming clkin signal has a different duty cycle. fifty-percent duty cycle means that the high and low times of each clock cycle are equal. the duty_cycle_correction attribute determines whether or not duty cycle correction is applied to the clk0, clk90, clk180 and clk270 outputs. if duty_cycle_correction is set to true, then the duty cycle of these four outputs is corrected to 50%. if duty_cycle_correction is set to false, then these outputs exhibit the same duty cycle as the clkin signal. figure 16 compares the characteristics of the dll?s output signals to those of the clkin signal. 1. the clk2x output generates a 25% duty cycle clock at the same frequency as the clkin signal until the dll has achieved lock. 2. the duty cycle of the clkdv outputs may differ somewhat from 50% (i.e., the signal will be high for less than 50% of the per iod) when the clkdv_divide attribute is set to a non-integer value and the dll is operating in the high frequency mode. figure 16: characteristics of the dll clock outputs output signal - duty cycle is always corrected output signal - attribute corrects duty cycle phase: input signal (30% duty cycle) 0 o 90 o 180 o 270 o 0 o 90 o 180 o 270 o 0 o duty_cycle_correction = false duty_cycle_correction = true ds099-2_10_031303 clk2x clk2x180 clkin clkdv (1) clk0 clk90 clk180 clk270 clk0 clk90 clk180 clk270 t notes: 1. the dll attribute clkdv_divide is set to 2.
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 25 advance product specification 1-800-255-7778 r digital frequency synthesizer (dfs) the dfs component generates clock signals the frequency of which is a product of the clock frequency at the clkin input and a ratio of two user-determined integers. because of the wide range of possible output frequencies such a ratio permits, the dfs feature provides still further flexibility than the dll?s basic synthesis options as described in the pre- ceding section. the dfs component?s two dedicated out- puts, clkfx and clkfx180, are defined in ta bl e 1 5 . the signal at the clkfx180 output is essentially an inver- sion of the clkfx signal. these two outputs always exhibit a 50% duty cycle. this is true even when the clkin signal does not. these dfs clock outputs are driven at the same time as the dll?s seven clock outputs. the numerator of the ratio is the integer value assigned to the attribute clkfx_multiply and the denominator is the integer value assigned to the attribute clkfx_divide. these attributes are described in ta bl e 1 4 . the output frequency (f clkfx ) can be expressed as a func- tion of the incoming clock frequency (f clkin ) as follows: f clkfx = f clkin *(clkfx_multiply/clkfx_divide) (3) regarding the two attributes, it is possible to assign any combination of integer values, provided that two conditions are met: 1. the two values fall within their corresponding ranges, as specified in ta b l e 1 4 . 2. the f clkfx frequency calculated from the above expression accords with the dcm?s operating frequency specifications. for example, if clkfx_multiply = 5 and clkfx_divide = 3, then the frequency of the output clock signal would be 5/3 that of the input clock signal. dfs frequency modes the dfs supports two operating modes, high frequency and low frequency, with each specified over a different clock frequency range. the dfs_frequency_mode attribute chooses between the two modes. when the attribute is set to low, the low frequency mode permits the two dfs outputs to operate over a low-to-moderate fre- quency range. when the attribute is set to high, the high frequency mode allows both these outputs to operate at the highest possible frequencies. dfs with or without the dll the dfs component can be used with or without the dll component: without the dll, the dfs component multiplies or divides the clkin signal frequency according to the respective clkfx_multiply and clkfx_divide values, generating a clock with the new target frequency on the clkfx and clkfx180 outputs. though classified as belonging to the dll component, the clkin input is shared with the dfs component. this case does not employ feedback loop; therefore, it cannot correct for clock distribution delay. with the dll, the dfs operates as described in the preced- ing case, only with the additional benefit of eliminating the clock distribution delay. in this case, a feedback loop from the clk0 output to the clkfb input must be present. the dll and dfs components work together to achieve this phase correction as follows: given values for the clkfx_multiply and clkfx_divide attributes, the dll selects the delay element for which the output clock edge coincides with the input clock edge whenever mathemati- cally possible. for example, when clkfx_multiply = 5 and clkfx_divide = 3, the input and output clock edges will coincide every three input periods, which is equivalent in time to five output periods. smaller clkfx_multiply and clkfx_divide values achieve faster lock times. with no factors common to the two attributes, alignment will occur once with every number of cycles equal to the clkfx_divide value. therefore, it is recommended that the user reduce these values by factor- ing wherever possible. for example, given clkfx_multiply = 9 and clkfx_divide = 6, removing a factor of three yields clkfx_multiply = 3 and clkfx_divide = 2. while both value-pairs will result in the multiplication of clock frequency by 3/2, the latter value-pair will enable the dll to lock more quickly. table 14: dfs attributes attribute description values dfs_frequency_mode chooses between high frequency and low frequency modes low, high clkfx_multiply frequency multiplier constant integer from 2 to 32 clkfx_divide frequency divisor constant integer from 1 to 32 table 15: dfs signals signal direction description clkfx output multiplies the clkin frequency by the attribute-value ratio (clkfx_multiply/clkfx_divide) to generate a clock signal with a new target frequency. clkfx180 output generates a clock signal with same frequency as clkfx, only shifted 180 out-of-phase.
spartan-3 1.2v fpga family: functional description 26 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r dfs clock output connections there are two basic cases that determine how to connect the dfs clock outputs: on-chip and off-chip, which are illus- trated in figure 15a and figure 15c , respectively. this is similar to what has already been described for the dll com- ponent. see the dll clock output and feedback con- nections , page 22 section. in the on-chip case, it is possible to connect either of the dfs?s two output clock signals through general routing resources to the fpga?s internal registers. either a global clock buffer (bufg) or a bufgmux affords access to the global clock network. the optional feedback loop is formed in this way, routing clk0 to a global clock net, which in turn drives the clkfb input. in the off-chip case, the dfs?s two output clock signals, plus clk0 for an optional feedback loop, can exit the fpga using output buffers (obuf) to drive a clock network plus registers on the board. the feedback loop is formed by feeding the clk0 signal back into the fpga using an ibufg, which directly accesses the global clock network, or an ibuf. then, the global clock net is connected directly to the clkfb input. phase shifter (ps) the dcm provides two approaches to controlling the phase of a dcm clock output signal relative to the clkin signal: first, there are nine clock outputs that employ the dll to achieve a desired phase relationship: clk0, clk90, clk180, clk270, clk2x, clk2x180, clkdv clkfx, and clkfx180. these outputs afford ?coarse? phase control. the second approach uses the ps component described in this section to provide a still finer degree of control. the ps component accomplishes this by introducing a "fine phase shift" (t ps ) between the clkfb and clkin signals inside the dll component. the user can control this fine phase shift down to a resolution of 1/256 of a clkin cycle or one tap delay (dcm_tap), whichever is greater. when in use, the ps component shifts the phase of all nine dcm clock output signals together. if the ps component is used together with a dcm clock output such as the clk90, clk180, clk270, clk2x180 and clkfx180, then the fine phase shift of the former gets added to the coarse phase shift of the latter. ps component enabling and mode selection the clkout_phase_shift attribute enables the ps component for use in addition to selecting between two operating modes. as described in ta b l e 1 6 , this attribute has three possible values: none, fixed and variable. when clkout_phase_shift is set to none, the ps component is disabled and its inputs, psen, psclk, and psincdec, must be tied to gnd. the set of waveforms in figure 17a shows the disabled case, where the dll main- tains a zero-phase alignment of signals clkfb and clkin upon which the ps component has no effect. the ps com- ponent is enabled by setting the attribute to either the fixed or variable values, which select the fixed phase mode and the variable phase mode, respectively. these two modes are described in the sections that follow determining the fine phase shift the user controls the phase shift of clkfb relative to clkin by setting and/or adjusting the value of the phase_shift attribute. this value must be an integer ranging from ?255 to +255. the ps component uses this value to calculate the desired fine phase shift (t ps ) as a fraction of the clkin period (t clkin ). given values for phase-shift and t clkin , it is possible to calculate t ps as follows: t ps = (phase_shift/256)*t clkin (4) both the fixed phase and variable phase operating modes employ this calculation. if the phase_shift value is zero, then clkfb and clkin will be in phase, the same as when the ps component is disabled. when the phase_shift value is positive, the clkfb signal will be shifted later in time with respect to clkin. if the attribute value is negative, the clkfb signal will be shifted earlier in time with respect to clkin. the fixed phase mode this mode fixes the desired fine phase shift to a fraction of the t clkin , as determined by equation (4) and its user-selected phase_shift value p. the set of wave- forms in figure 17b illustrates the relationship between clkfb and clkin in the fixed phase mode. in the fixed phase mode, the psen, psclk and psincdec inputs are not used and must be tied to gnd. table 16: ps attributes attribute description values clkout_phase_shift disables ps component or chooses between fixed phase and variable phase modes. none, fixed, variable phase_shift determines size and direction of initial fine phase shift. integers from ?255 to +255 (1) notes: 1. the practical range of values will be less when t clkin > fine_shift_range in the fixed phase mode, also when t clkin > (fine_shift_range)/2 in the variable phase mode. the fine _shift_range represents the sum total delay of all taps.
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 27 advance product specification 1-800-255-7778 r figure 17: phase shifter waveforms ds099-2_11_031303 clkin clkfb * t clkin p 256 b. clkout_phase_shift = fixed * t clkin p 256 shift range over all p values: ?255 +255 shift range over all p values: 0 0 ?255 +255 shift range over all n values: 0 ?255 +255 clkin clkfb before decrement c. clkout_phase_shift = variable clkfb after decrement * t clkin n 256 clkin clkfb a. clkout_phase_shift = none notes: 1. p represents the integer value ranging from ?255 to +255 to which the phase_shift attribute is assigned. 2. n is an integer value ranging from ?255 to +255 that represents the net phase shift effect from a series of increment and/or decrement operations. n = {total number of increments} ? {total number of decrements} a positive value for n indicates a net increment; a negative value indicates a net decrement.
spartan-3 1.2v fpga family: functional description 28 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r the variable phase mode the ?variable phase? mode dynamically adjusts the fine phase shift over time using three inputs to the ps compo- nent, namely psen, psclk and psincdec, as defined in ta b l e 1 7 . just following device configuration, the ps component ini- tially determines t ps by evaluating equation (4) for the value assigned to the phase_shift attribute. then to dynamically adjust that phase shift, use the three ps inputs to increase or decrease the fine phase shift. psincdec is synchronized to the psclk clock signal, which is enabled by asserting psen. it is possible to drive the psclk input with the clkin signal or any other clock signal. a request for phase adjustment is entered as follows: for each psclk cycle that psincdec is high, the ps component adds 1/256 of a clkin cycle to t ps . similarly, for each enabled psclk cycle that psincdec is low, the ps component subtracts 1/256 of a clkin cycle from t ps . the phase adjustment may require as many as 100 clkin cycles plus three psclk cycles to take effect, at which point the output psdone goes high for one psclk cycle. this pulse indicates that the ps component has finished the present adjustment and is now ready for the next request. asserting the reset (rst) input, returns t ps to its original shift time, as determined by the phase_shift attribute value. the set of waveforms in figure 17c illustrates the relationship between clkfb and clkin in the variable phase mode. the status logic component the status logic component not only reports on the state of the dcm but also provides a means of resetting the dcm to an initial known state. the signals associated with the sta- tus logic component are described in ta bl e 1 8 . as a rule, the reset (rst) input is asserted only upon con- figuring the device or changing the clkin frequency. a dcm reset does not affect attribute values (e.g., clkfx_multiply and clkfx_divide). if not used, rst must be tied to gnd. the eight bits of the status bus are defined in ta b l e 1 9 . table 17: signals for variable phase mode signal direction description psen (1) input enables psclk for variable phase adjustment. psclk (1) input clock to synchronize phase shift adjustment. psincdec (1) input chooses between increment and decrement for phase adjustment. it is synchronized to the psclk signal. psdone output goes high to indicate that present phase adjustment is complete and ps component is ready for next phase adjustment request. it is synchronized to the psclk signal. notes: 1. it is possible to program this input for either a true or inverted polarity table 18: status logic signals signal direction description rst input a high resets the entire dcm to its initial power-on state. initializes the dll taps for a delay of zero. sets the locked output low. this input is asynchronous. status[7:0] output the bit values on the status bus provide information regarding the state of dll and ps operation locked output indicates that the clkin and clkfb signals are in phase by going high. the two signals are out-of-phase when low.
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 29 advance product specification 1-800-255-7778 r stabilizing dcm clocks before user mode it is possible to delay the completion of device configuration until after the dll has achieved a lock condition using the startup_wait attribute described in ta bl e 2 0 . this option ensures that the fpga does not enter user mode ? i.e., begin functional operation ? until all system clocks generated by the dcm are stable. in order to achieve the delay, it is necessary to set the attribute to true as well as set the bitgen option lck_cycle to one of the six cycles making up the startup phase of configuration. the selected cycle defines the point at which configuration will halt until the locked output goes high. global clock network spartan-3 devices have eight global clock inputs called gclk0 - gclk7. these inputs provide access to a low-capacitance, low-skew network that is well-suited to carrying high-frequency signals. the spartan-3 clock net- work is shown in figure 18 . gclk0 through gclk3 are placed at the center of the die?s bottom edge. gclk4 through gclk7 are placed at the center of the die?s top edge. it is possible to route each of the eight global clock inputs to any clb on the die. eight global clock multiplexers (also called bufgmux ele- ments) are provided that accept signals from global clock inputs and route them to the internal clock network as well as dcms. four bufgmux elements are placed at the cen- ter of the die?s bottom edge, just above the gclk0 - gclk4 inputs. the remaining four bufgmux elements are placed at the center of the die?s top edge, just below the gclk4 - gclk7 inputs. each bufgmux element is a 2-to-1 multiplexer that can receive signals from any of the four following sources: 1. one of the four global clock inputs on the same side of the die ? top or bottom ? as the bufgmux element in use. 2. any of four nearby horizontal double lines. 3. any of four outputs from the dcm in the right-hand quadrant that is on the same side of the die as the bufgmux element in use. 4. any of four outputs from the dcm in the left-hand quadrant that is on the same side of the die as the bufgmux element in use. sources 3 and 4 are not available on the xc3s50 die that lacks dcms. each bufgmux can switch incoming clock signals to two possible destinations: 1. the vertical spine belonging to the same side of the die ? top or bottom ? as the bufgmux element in use. the two spines ? top and bottom ? each comprise four vertical clock lines, each running from one of the table 19: dcm status bus bit name description 0 phase shift overflow a value of 1 indicates a phase shift overflow when one of two conditions occur: incrementing (or decrementing) tps beyond 255/256 of a clkin cycle. the dll is producing its maximum possible phase shift (i.e., all delay taps are active). (1) 1 clkin activity a value of 1 indicates that the clkin signal is not toggling. a value of 0 indicates toggling. this bit functions only when the clkfb input is connected. (2) 2 reserved - 3 reserved - 4 reserved - 5 reserved - 6 reserved - 7 reserved - notes: 1. the dll phase shift with all delay taps active is specified as the parameter fine_shift_range. 2. if only the dfs clock outputs are used, but none of the dll clock outputs, this bit will not go high when the clkin signal st ops. table 20: status attributes attribute description values startup_wait delays transition from configuration to user mode until lock condition is achieved. true, false
spartan-3 1.2v fpga family: functional description 30 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r bufgmux elements on the same side towards the center of the die. at the center of the die, clock signals reach the eight-line horizontal spine, which spans the width of the die. in turn, the horizontal spine branches out into a subsidiary clock interconnect that accesses the clbs. 2. the clock input of either dcm on the same side of the die ? top or bottom ? as the bufgmux element in use. a global clock input is placed in a design using either a bufgmux element or the bufg (global clock buffer) ele- ment. for the purpose of minimizing the dynamic power dis- sipation of the clock network, the xilinx development software automatically disables all clock line segments that a design does not use. figure 18: spartan-3 clock network (top view) 4 4 4 4 4 4 4 8 8 4 4 8 8 horizontal spine top spine bottom spine 4 dcm dcm dcm dcm array dependent array dependent ds099-2_18_070203 4 bufgmux gclk2 gclk3 gclk0 gclk1 4 bufgmux gclk6 gclk4 gclk7 gclk5
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 31 advance product specification 1-800-255-7778 r interconnect interconnect (or routing) passes signals among the various functional elements of spartan-3 devices. there are four kinds of interconnect: long lines, hex lines, double lines, and direct lines. long lines connect to one out of every six clbs (see figure 19a ). because of their low capacitance, these lines are well-suited for carrying high-frequency signals with min- imal loading effects (e.g. skew). if all eight global clock inputs are already committed and there remain additional clock signals to be assigned, long lines serve as a good alternative. hex lines connect one out of every three clbs (see figure 19b ). these lines fall between long lines and dou- ble lines in terms of capability: hex lines approach the high-frequency characteristics of long lines at the same time, offering greater connectivity. double lines connect to every other clb (see figure 19c ). compared to the types of lines already discussed, double lines provide a higher degree of flexibility when making con- nections. direct lines afford any clb direct access to neighboring clbs (see figure 19d ). these lines are most often used to conduct a signal from a "source" clb to a double, hex, or long line and then from the longer interconnect back to a direct line accessing a "destination" clb. figure 19: types of interconnect clb clb clb clb clb clb 66 666 clb clb clb clb ds099-2_19_040103 (a) long line clb clb clb clb clb clb clb 8 ds099-2_20_040103 (b) hex line clb 2 clb clb ds099-2_21_040103 clb clb clb clb clb clb clb clb clb ds099-2_22_040103 (d) direct lines (c) double line
spartan-3 1.2v fpga family: functional description 32 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r configuration spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory. configuration is carried out using a subset of the device pins, some of which are "dedicated" to one function only, while others, indicated by the term "dual-purpose", can be re-used as general-purpose user i/os once configu- ration is complete. depending on the system design, several configuration modes are supported, selectable via mode pins. the mode pins m0, m1, and m2 are dedicated pins. the mode pin set- tings are shown in ta b l e 2 1 . an additional pin, hswap_en, is used in conjunction with the mode pins to select whether user i/o pins have pull-ups during configuration. by default, hswap_en is tied high (internal pull-up) which shuts off the pull-ups on the user i/o pins during configuration. when hswap_en is tied low, user i/os have pull-ups during configuration. other dedi- cated pins are cclk (the configuration clock pin), done, prog_b, and the boundary-scan pins: tdi, tdo, tms, and tck. depending on the configuration mode chosen, cclk can be an output generated by the fpga, or an input accepting an externally generated clock. a persist option is available which can be used to force the configuration pins to retain their configuration function even after device configuration is complete. if the persist option is not selected then the configuration pins with the exception of cclk, prog_b, and done can be used as user i/o in normal operation. the persist option does not apply to the boundary-scan related pins. the persist feature is valuable in applications that readback configuration data after enter- ing the user mode. ta b l e 2 2 lists the total number of bits required to configure each fpga as well as the proms suitable for storing those bits. see ds123 : platform flash in-system programmable configuration proms data sheet for more information. the standard confi guration interface configuration signals belong to one of two different catego- ries: dedicated or dual-purpose. which category deter- mines which of the fpga?s power rails supplies the signal?s driver and, thus, helps describe the electrical at the pin. the dedicated configuration pins include prog_b, hswap_en, tdi, tms, tck, tdo, cclk, done, and m0-m2. these pins use the v ccaux lines for power. the dual-purpose configuration pins comprise init_b, dout, busy, rdwr_b, cs_b, and din/d0-d7. each of these pins, according to its bank placement, uses the v cco lines for either bank 4 (vcco_4) or bank 5 (vcco_5). all the signals used in the serial configuration modes rely on vcco_4 power. signals used in the parallel configuration modes and readback require from vcco_5 as well as from vcco_4. both the dedicated and dual-purpose signals described above constitute the configuration interface. in the standard case, this interface is 2.5v-lvcmos-compatible. this means that 2.5v is applied to the v ccaux , vcco_4, and vcco_5 lines (this last in the parallel or readback case only). one need only apply 2.5 volts to these v cco lines from power-on to the end of configuration. upon entering the user mode, it is possible to switch to supply voltage per- mitting signal swings other than 2.5v. table 21: spartan-3 configuration mode pin settings configuration mode (1) m0 m1 m2 synchronizing clock data width serial dout (2) master serial 0 0 0 cclk output 1 yes slave serial 1 1 1 cclk input 1 yes master parallel 1 1 0 cclk output 8 no slave parallel 0 1 1 cclk input 8 no jtag 1 0 1 tck input 1 no notes: 1. the voltage levels on the m0, m1, and m2 pins select the configuration mode. 2. the daisy chain is possible only in the serial modes when dout is used. table 22: spartan-3 configuration data device file sizes xilinx platform flash prom serial configuration parallel configuration xc3s50 439,264 xcf01s xcf08p xc3s200 1,047,616 xcf01s xcf08p xc3s400 1,699,136 xcf02s xcf08p xc3s1000 3,223,488 xcf04s xcf08p xc3s1500 5,214,784 xcf08p xcf08p xc3s2000 7,673,024 xcf08p xcf08p xc3s4000 11,316,864 xcf16p xcf16p xc3s5000 13,271,936 xcf16p xcf16p
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 33 advance product specification 1-800-255-7778 r 3.3v-tolerant configuration interface it is possible to achieve 3.3v-tolerance at the configuration interface simply by adding a few external resistors. this approach may prove useful when it is undesirable to switch the vcco_4 and vcco_5 voltages from 2.5v to 3.3v after configuration. the 3.3v-tolerance is implemented as follows (a similar approach can be used for other supply voltage levels): first, to power the dual-purpose configuration pins, apply 3.3v to the vcco_4 and (as needed) the vcco_5 lines. this scales the output voltages and input thresholds associ- ated with these pins so that they become 3.3v-compatible. second, to power the dedicated configuration pins, apply 2.5v to the v ccaux lines (the same as for the standard interface). in order to achieve 3.3v-tolerance, the dedicated inputs will require series resistors that limit the incoming current to 10ma or less. the dedicated outputs will need pull-up resistors to ensure adequate noise margin when the fpga is driving a high logic level into another device?s 3.3v receiver. choose a power regulator or supply that can toler- ate reverse current on the v ccaux lines. configuration modes spartan-3 supports the following five configuration modes: slave serial mode master serial mode slave parallel mode master parallel mode boundary-scan (jtag) mode (ieee 1532/ieee 1149.1) slave serial mode in slave serial mode, the fpga receives configuration data in bit-serial form from a serial prom or other serial source of configuration data. the fpga on the far right of figure 20 is set for the slave serial mode. the cclk pin on the fpga is an input in this mode. the serial bitstream must be setup at the din input pin a short time before each rising edge of the externally generated cclk. multiple fpgas can be daisy-chained for configuration from a single source. after a particular fpga has been config- ured, the data for the next device is routed internally to the dout pin. the data on the dout pin changes on the rising edge of cclk. figure 20: connection diagram for master and slave serial configuration dout din cclk done init_b spartan-3 fpga master prog_b din cclk done init_b spartan-3 fpga slave prog_b ds099_23_041103 d0 clk ce oe/reset cf platform flash prom xcf0xs or xcfxxp v ccint 1.2v v ccaux v cco bank 4 2.5v 2.5v 4.7k all 2.5v v ccaux v ccint v cco bank 4 1.2v 3.3v v cc v ccj v cco 2.5v 2.5v m0 m1 m2 m0 m1 m2 gnd gnd gnd notes: 1. there are two ways to use the done line. first, one may set the bitgen option drivedone to "yes" only for the last fpga to be configured in the chain shown above (or for the single fpga as may be the case). this enables the done pin to drive high; thus, no pull-up resistor is necessary. drivedone is set to "no" for the remaining fpgas in the chain. second, drivedone can be set to "no" for all fpgas. then all done lines are open-drain and require the pull-up resistor shown in grey. in most cases, a value between 3.3k to 4.7k is sufficient. however, when using done synchronously with a long chain of fpgas, cumulative capacitance may necessitate lower resistor values (e.g. down to 330 ) in order to ensure a rise time within one clock cycle. 2. for information on how to program the fpga using 3.3v signals and power, see 3.3v-tolerant configuration interface .
spartan-3 1.2v fpga family: functional description 34 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r slave serial mode is selected by applying <111> to the mode pins (m0, m1, and m2). a weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. master serial mode in master serial mode, the cclk pin is an output pin. the fpga just to the right of the prom in figure 20 is set for master serial mode. it is the fpga that drives the configu- ration clock on the cclk pin to a xilinx serial prom which in turn feeds bit-serial data to the din input. the fpga accepts this data on each rising cclk edge. after the fpga has been loaded, the data for the next device in a daisy-chain is presented on the dout pin after the rising cclk edge. the interface is identical to slave serial except that an inter- nal oscillator is used to generate the configuration clock (cclk). a wide range of frequencies can be selected for cclk which always starts at a default frequency of 6 mhz. configuration bits then switch cclk to a higher frequency for the remainder of the configuration. slave parallel mode the parallel modes support the fastest configuration. byte-wide data is written into the fpga with a busy flag controlling the flow of data. an external source provides 8-bit-wide data, cclk, an active-low chip select (cs_b) signal and an active-low write signal (rdwr_b). if busy is asserted (high) by the fpga, the data must be held until busy goes low. data can also be read using the slave parallel mode. if rdwr_b is asserted, configuration data is read out of the fpga as part of a readback operation. after configuration, it is possible to use any of the multipur- pose pins (din/d0-d7, dout/busy, initb, cs_b, and rdwr_b) as user i/os. to do this, simply set the bitgen option persist to no and assign the desired signals to multi- purpose configuration pins using the xilinx development software. alternatively, it is possible to continue using the configuration port (e.g. all configuration pins taken together) when operating in the user mode. this is accomplished by setting the persist option to ye s . multiple fpgas can be configured using the slave parallel mode and can be made to start-up simultaneously. figure 21 shows the device connections. to configure mul- tiple devices in this way, wire the individual cclk, data, rdwr_b, and busy pins of all the devices in parallel. the individual devices are loaded separately by deasserting the cs_b pin of each device in turn and writing the appropriate data.
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 35 advance product specification 1-800-255-7778 r figure 21: connection diagram for slave parallel configuration prog_b init_b done spartan-3 slave init_b d[0:7] cclk rdwr_b busy cs_b prog_b done cs_b spartan-3 slave init_b gnd d[0:7] cclk rdwr_b busy cs_b d[0:7] cclk rdwr_b busy prog_b done cs_b ds099_24_041103 2.5v m1 m2 m0 2.5v m1 m2 m0 2.5v v ccaux v cco banks 4 & 5 v ccint 1.2v 4.7k ? 4.7k ? 2.5v v ccaux v cco banks 4 & 5 v ccint 1.2v 2.5v gnd notes: 1. there are two ways to use the done line. first, one may set the bitgen option drivedone to "yes" only for the last fpga to be configured in the chain shown above (or for the single fpga as may be the case). this enables the done pin to drive high; thus, no pull-up resistor is necessary. drivedone is set to "no" for the remaining fpgas in the chain. second, drivedone can be set to "no" for all fpgas. then all done lines are open-drain and require the pull-up resistor shown in grey. in most cases, a value between 3.3k ? to 4.7k ? is sufficient. however, when using done synchronously with a long chain of fpgas, cumulative capacitance may necessitate lower resistor values (e.g. down to 330 ? ) in order to ensure a rise time within one clock cycle. 2. if the fpgas use different configuration data files, configure them in sequence by first asserting the cs_b of one fpga then asserting the cs_b of the other fpga. 3. for information on how to program the fpga using 3.3v signals and power, see 3.3v-tolerant configuration interface .
spartan-3 1.2v fpga family: functional description 36 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r master parallel mode in this mode, the device is configured byte-wide on a cclk supplied by the fpga. timing is similar to the slave parallel mode except that cclk is supplied by the fpga. the device connections are shown in figure 22 . boundary-scan (jtag) mode in boundary-scan mode, dedicated pins are used for con- figuring the fpga. the configuration is done entirely through the ieee 1149.1 test access port (tap). fpga configuration using the boundary-scan mode is compliant with the ieee 1149.1-1993 standard and the new ieee 1532 standard for in-system configurable (isc) devices. configuration through the boundary-scan port is always available, independent of the mode selection. selecting the boundary-scan mode simply turns off the other modes. configuration sequence the configuration of spartan-3 devices is a three-stage pro- cess that occurs after power-on reset or the assertion of prog_b. por occurs after the v ccint , v ccaux , and v cco bank 4 supplies have reached their respective maximum input threshold levels (see ta bl e 7 in module 3: dc and switching characteristics ). after por, the three-stage process begins. first, the configuration memory is cleared. next, con- figuration data is loaded into the memory, and finally, the logic is activated by a start-up process. a flow diagram for the configuration sequence of the serial and parallel modes is shown in figure 23 . the flow diagram for the bound- ary-scan configuration sequence appears in figure 24 . figure 22: connection diagram for master parallel configuration spartan-3 master d[0:7] cclk prog_b done init_b data[0:7] cclk rdwr_b cs_b cf ce oe/reset platform flash prom ds099_25_041103 2.5v v ccaux v cco banks 4 & 5 v ccint 1.2v gnd gnd 3.3v v cc v ccj v cco 2.5v xcfxxp 2.5v all 4.7k notes: 1. there are two ways to use the done line. first, one may set the bitgen option drivedone to "yes" only for the last fpga to be configured in the chain shown above (or for the single fpga as may be the case). this enables the done pin to drive high; thus, no pull-up resistor is necessary. drivedone is set to "no" for the remaining fpgas in the chain. second, drivedone can be set to "no" for all fpgas. then all done lines are open-drain and require the pull-up resistor shown in grey. in most cases, a value between 3.3k to 4.7k is sufficient. however, when using done synchronously with a long chain of fpgas, cumulative capacitance may necessitate lower resistor values (e.g. down to 330 ) in order to ensure a rise time within one clock cycle.
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 37 advance product specification 1-800-255-7778 r figure 23: configuration flow diagram for the serial and parallel modes sample mode pins no no no yes yes yes clear configuration memory power-on set prog_b low after power-on yes no crc correct? yes no reconfigure? load configuration data frames init_b goes low. abort start-up start-up sequence user mode init_ b = high? prog_b = low ds099_26_041103 v ccint >1v and v ccaux > 2v and v cco bank 4 > 1v
spartan-3 1.2v fpga family: functional description 38 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r figure 24: boundary-scan configuration flow diagram sample mode pins (jtag port becomes available) clear configuration memory no no no yes yes yes yes no yes power-on crc correct? load cfg_in instruction shutdown sequence reconfigure? load jstart instruction synchronous tap reset (clock five 1's on tms) start-up sequence user mode init_b = high? prog_b = low load jshutdown instruction no ds099_27_041103 load configuration data frames v ccint >1v and v ccaux > 2v and v cco bank 4 > 1v init_b goes low. abort start-up set prog_b low after power-on
spartan-3 1.2v fpga family: functional description ds099-2 (v1.2) july 11, 2003 www.xilinx.com 39 advance product specification 1-800-255-7778 r configuration is automatically initiated after power-on unless it is delayed by the user. init_b is an open-drain line that the fpga holds low during the clearing of the configu- ration memory. extending the time that the pin is low causes the configuration sequencer to wait. thus, configu- ration is delayed by preventing entry into the phase where data is loaded. the configuration process can also be initiated by asserting the prog_b pin. the end of the memory-clearing phase is signaled by the init_b pin going high. at this point, the con- figuration data is written to the fpga. the fpga holds the global set/reset (gsr) signal active throughout configura- tion, keeping all flip-flops on the device in a reset state. the completion of the entire process is signaled by the done pin going high. the default start-up sequence, shown in figure 25 , serves as a transition to the user mode. the default start-up sequence is that one cclk cycle after done goes high, the global three-state signal (gts) is released. this per- mits device outputs to which signals have been assigned to become active. one cclk cycle later, the global write enable (gwe) signal is released. this permits the internal storage elements to begin changing state in response to the design logic and the user clock. the relative timing of configuration events can be changed via the bitgen options in the xilinx development software. in addition, the gts and gwe events can be made depen- dent on the done pins of multiple devices all going high, forcing the devices to start synchronously. the sequence can also be paused at any stage, until lock has been achieved on any dcm. readback using slave parallel mode, configuration data from the fpga can be read back. readback is supported only in the slave parallel and boundary-scan modes. along with the configuration data, it is possible to read back the contents of all registers, distributed selectram, and block ram resources. this capability is used for real-time debugging. figure 25: default start-up sequence start-up clock default cycles sync-to-done 0123 4567 01 done high 23 4567 phase start-up clock phase done gts gsr gwe ds099_028_040803 done gts gsr gwe notes: 1. the bitgen option startupclk in the xilinx development software selects the cclk input, tck input, or a user-designated global clock input (the gclk0 - gclk7 pins) for receiving the clock signal that synchronizes start-up.
spartan-3 1.2v fpga family: functional description 40 www.xilinx.com ds099-2 (v1.2) july 11, 2003 1-800-255-7778 advance product specification 40 r revision history the spartan-3 family data sheet ds099-1 , spartan-3 1.2v fpga family: introduction and ordering information (module 1) ds099-2, spartan-3 1.2v fpga family: functional description (module 2) ds099-3, spartan-3 1.2v fpga family: dc and switching characteristics (module 3) ds099-4 , spartan-3 1.2v fpga family: pinout descriptions (module 4) date version no. description 04/11/03 1.0 initial xilinx release 05/19/03 1.1 added block ram column, dcms, and multipliers to xc3s50 descriptions. 07/11/03 1.2 explained the configuration port persist option in slave parallel mode section. updated figure 2 and double-data-rate transmission section to indicate that ddr clocking for the xcs350 is the same as that for all other spartan-3 devices. updated description of i/o voltage tolerance in esd protection section. in ta b l e 6 , changed input termination type for dci version of the lvcmos standard to none . added additional flexibility for making dll connections in figure 15 and accompanying text. in the configuration section, inserted an explanation of how to choose power supplies for the configuration interface, including guidelines for achieving 3.3v-tolerance.
ds099-3 (v1.3) march 4, 2004 www.xilinx.com 1 advance product specification 1-800-255-7778 ? 2003-2004 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. dc electrical characteristics in this section, some specifications may be designated as advance or preliminary. these terms are defined as fol- lows: advance: initial estimates based on simulation, early char- acterization, and/or extrapolation from the characteristics of other families. values are subject to change. use as esti- mates, not for production. preliminary: based on characterization. further changes are not expected. all parameter limits are representative of worst-case supply voltage and junction temperature conditions. the following applies unless otherwise noted: the parameter values pub- lished in this module apply to all spartan-3 devices. ac and dc characteristics are specified using the same numbers for both commercial and industrial grades. all parameters representing voltages are measured with respect to gnd. some specifications list different values for one or more die revisions. all presently available spartan-3 devices are classified as revision 0. future updates to this module will introduce further die revisions as needed. 040 spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 00 advance product specification r table 1: absolute maximum ratings symbol description conditions min max units v ccint internal supply voltage ?0.5 1.32 v v ccaux auxiliary supply voltage ?0.5 3.00 v v cco output driver supply voltage ?0.5 3.75 v v ref (2) input reference voltage ?0.5 v cco +0.5 v v in (2) voltage applied to all user i/o pins and dual-purpose pins (3) driver in a high-impedance state ?0.5 v cco +0.5 v voltage applied to all dedicated pins (4) ?0.5 v ccaux +0.5 v t j junction temperature v cco < 3.0v - 125 c v cco > 3.0v - 105 c t sol (5) soldering temperature - 220 c t stg storage temperature ?65 150 c notes: 1. stresses beyond those listed under absolute maximum ratings will cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the recommended operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time adversely affects device reliability. 2. ta bl e 5 specifies the range of values for v cco and v ccaux , which are used to determine the limits of this parameter. 3. all user i/o and dual-purpose pins (din/d0, d1?d7, cs _b, rdwr_b, busy/dout, and init_b) draw power from the v cco power rail of the associated bank. 4. all dedicated pins (m0?m2, cclk, prog_b, done, hswap_en, tck, tdi, tdo, and tms) draw power from the v ccaux rail (2.5v). for information concerning the use of 3.3v signals, see the 3.3v-tolerant configuration interface section in module 2: functional description . 5. for soldering guidelines, see the information on "packaging and thermal characteristics" at www.xilinx.com .
spartan-3 fpga family: dc and switching characteristics 2 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 2: supply voltage thresholds for power-on reset symbol description min max units v ccintt threshold for the v ccint supply 0.4 1.0 v v ccauxt threshold for the v ccaux supply 0.8 2.0 v v cco4t threshold for the v cco bank 4 supply 0.4 1.0 v notes: 1. v ccint , v ccaux , and v cco supplies may be applied in any order. 2. to ensure successful power-on, v ccint , v cco bank 4, and v ccaux supplies must rise through their respective threshold-voltage ranges with no dips at any point. table 3: other power-on requirements symbol description device revision min max units t cco v cco ramp time for all eight banks 0 xc3s200, xc3s400, and xc3s1500 in the ft and fg packages (1) 600 - s all other devices 2.0 - ms future to be improved - notes: 1. this specification is based on characterization. 2. at present, there are no ramp requirements for the v ccint and v ccaux supplies. table 4: power voltage levels necessary for preserving ram contents symbol description min units v drint v ccint level required to retain ram data 1.0 v v draux v ccaux level required to retain ram data 2.0 v notes: 1. ram contents include configuration data. 2. the level of the v cco supply has no effect on data retention.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 3 advance product specification 1-800-255-7778 40 r table 5: general recommended operating conditions symbol description min nom max units t j junction temperature commercial 0 - 85 c industrial ?40 - 100 c v ccint internal supply voltage 1.140 1.200 1.260 v v cco (1) output driver supply voltage 1.140 - 3.450 v v ccaux auxiliary supply voltage 2.375 2.500 2.625 v notes: 1. the v cco range given here spans the lowest and highest operating voltages of all supported i/o standards. the recommended v cco range specific to each of the single-ended i/o standards is given in table 8 , and that specific to the differential standards is given in ta bl e 1 0 . table 6: general dc characteristics of user i/o, dual-purpose, and dedicated pins symbol description test conditions device revision min typ max units i l leakage current at user i/o, dual-purpose, and dedicated pins driver is in a high-impedance state, v in = 0v or v cco max, sample-tested 0v cco > 3.0v ?25 - +25 a v cco < 3.0v ?10 - +10 a i rpu (2) current through pull-up resistor at user i/o, dual-purpose, and dedicated pins v in =0, v cco = 3.3v 0 ?0.84 - ?2.35 ma v in =0, v cco = 3.0v ?0.69 - ?1.99 ma v in =0, v cco = 2.5v ?0.47 - ?1.41 ma v in =0, v cco = 1.8v ?0.21 - ?0.69 ma v in =0, v cco = 1.5v ?0.13 - ?0.43 ma v in =0, v cco = 1.2v ?0.06 - ?0.22 ma i rpd (2) current through pull-down resistor at user i/o, dual-purpose, and dedicated pins v in = v cco 0.37 - 1.67 ma i ref v ref current per pin 0 v cco > 3.0v ?25 - +25 a v cco < 3.0v ?10 - +10 a c in input capacitance all 3 - 10 pf notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 5 . 2. this parameter is based on characterization.
spartan-3 fpga family: dc and switching characteristics 4 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 7: quiescent supply current characteristics symbol description device commercial industrial units typmaxtypmax i ccintq quiescent v ccint supply current xc3s50 10.0 ma xc3s200 20.0 ma xc3s400 35.0 ma xc3s1000 65.0 ma xc3s1500 ma xc3s2000 ma xc3s4000 ma xc3s5000 ma i ccoq quiescent v cco supply current xc3s50 1.5 ma xc3s200 1.5 ma xc3s400 1.5 ma xc3s1000 1.5 ma xc3s1500 ma xc3s2000 ma xc3s4000 ma xc3s5000 ma i ccauxq quiescent v ccaux supply current xc3s50 7.0 ma xc3s200 15.0 ma xc3s400 20.0 ma xc3s1000 25.0 ma xc3s1500 ma xc3s2000 ma xc3s4000 ma xc3s5000 ma notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 5 . quiescent supply current is measured with all i/o drivers in a high-impedance state and with all pull-up/pull-down resistors at the i/o pads disabled. for typical values, the ambient temperature (t a ) is 25 c with v ccint = 1.2v, v cco = 2.5v, and v ccaux = 2.5v. the fpga is programmed with a "blank" configuration data file (i.e., a design with no functional elements instantiated). 2. there are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) the spartan-3 web power tool at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not require a netlist of the design. b) xpower, part of the xilinx development software, takes a netlist as input to provide more a ccurate maximum and typical estimates.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 5 advance product specification 1-800-255-7778 40 r table 8: recommended operating conditions for us er i/os using single-ended standards signal standard v cco v ref v il v ih min (v) nom (v) max (v) min (v) nom (v) max (v) max (v) min (v) gtl (2) - - - 0.74 0.8 0.86 v ref - 0.05 v ref + 0.05 gtl_dci - 1.2 - 0.74 0.8 0.86 v ref - 0.05 v ref + 0.05 gtlp (2) -- -0.8811.12v ref - 0.1 v ref + 0.1 gtlp_dci - 1.5 - 0.88 1 1.12 v ref - 0.1 v ref + 0.1 hstl_i, hstl_i_dci 1.4 1.5 1.6 0.68 0.75 0.9 v ref - 0.1 v ref + 0.1 hstl_iii, hstl_iii_dci 1.4 1.5 1.6 0.68 0.9 0.9 v ref - 0.1 v ref + 0.1 hstl_i_18, hstl_i_dci_18 1.7 1.8 1.9 - 0.9 - v ref - 0.1 v ref + 0.1 hstl_ii_18, hstl_ii_dci_18 1.7 1.8 1.9 - 0.9 - v ref - 0.1 v ref + 0.1 hstl_iii_18, hstl_iii_dci_18 1.7 1.8 1.9 - 1.1 - v ref - 0.1 v ref + 0.1 lvc mos 1 2 (3) 1.14 1.2 1.3 - - - 0.20v cco 0.70v cco lvc mos 1 5, lvdci_15, lvdci_dv2_15 (3) 1.4 1.5 1.6 - - - 0.20v cco 0.70v cco lvc mos 1 8, lvdci_18, lvdci_dv2_18 (3) 1.7 1.8 1.9 - - - 0.20v cco 0.70v cco lvc mos 2 5 (4) , lvdci_25, lvdci_dv2_25 (3) 2.3 2.5 2.7 - - - 0.7 1.7 lvc mos 3 3, lvdci_33, lvdci_dv2_33 (3) 3.0 3.3 3.45 - - - 0.8 2.0 lvttl 3.0 3.3 3.45 - - - 0.8 2.0 pci33_3 - 3.0 - - - - 0.30v cco 0.50v cco sstl18_i, sstl18_i_dci 1.65 1.8 1.95 0.825 0.9 0.975 v ref - 0.125 v ref + 0.125 sstl2_i, sstl2_i_dci 2.3 2.5 2.7 1.15 1.25 1.35 v ref - 0.15 v ref + 0.15 sstl2_ii, sstl2_ii_dci 2.3 2.5 2.7 1.15 1.25 1.35 v ref - 0.15 v ref + 0.15 notes: 1. descriptions of the symbols used in this table are as follows: v cco -- the supply voltage for output drivers as well as lvcmos, lvttl, and pci inputs v ref -- the reference voltage for setting the input switching threshold v il -- the input voltage that indicates a low logic level v ih -- the input voltage that indicates a high logic level 2. because the gtl and gtlp standards employ open-drain output buffers, v cco lines do not supply current to the i/o circuit, rather this current is provided using an external pull-up resistor connected from the i/o pin to a termination voltage (v tt ). nevertheless, the voltage applied to the associated v cco lines must always be at or above v tt and i/o pad voltages. 3. there is approximately 100 mv of hysteresis on inputs using any lvcmos standard. 4. all dedicated pins (m0-m2, cclk, prog_b, done, hswap_en, tck, tdi, tdo, and tms) use the lvcmos25 standard and draw power from the v ccaux rail (2.5v). the dual-purpose configuration pins (din/d0, d1-d7, cs_b, rdwr_b, busy/dout, and init_b) use the lvcmos25 standard before the user mode. for these pins, apply 2.5v to the v cco bank 4 and v cco bank 5 rails at power-on as well as throughout configuration. for information concerning the use of 3.3v signals, see the 3.3v-tolerant configuration interface section in module 2: functional description . 5. the global clock inputs have the following bank associations: gclk0 and gclk1 with bank 4, gclk2 and gclk3 with bank 5, gclk4 and gclk5 with bank 1, and gclk6 and gclk7 with bank 0. the signal standards assigned to the global clock lines (and i/os) of a given bank determine the v cco voltage for that bank.
spartan-3 fpga family: dc and switching characteristics 6 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 9: dc characteristics of user i/os using single-ended standards signal standard and current drive attribute (ma) test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v) gtl 32 - 0.4 - gtl_dci note 3 note 3 gtlp 36 - 0.6 - gtlp_dci note 3 note 3 hstl_i 8 ?8 0.4 v cco - 0.4 hstl_i_dci note 3 note 3 hstl_iii 24 ?8 0.4 v cco - 0.4 hstl_iii_dci note 3 note 3 hstl_i_18 8 ?8 0.4 v cco - 0.4 hstl_i_dci_18 note 3 note 3 hstl_ii_18 16 ?16 0.4 v cco - 0.4 hstl_ii_dci_18 note 3 note 3 hstl_iii_18 24 ?8 0.4 v cco - 0.4 hstl_iii_dci_18 note 3 note 3 lvcm os 12 (4) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 lvcm os 15 (4) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 12 12 ?12 lvdci_15, lvdci_dv2_15 note 3 note 3 lvcm os 18 (4) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 12 12 ?12 16 16 ?16 lvdci_18, lvdci_dv2_18 note 3 note 3 lvcm os 25 (4,5) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 12 12 ?12 16 16 ?16 24 24 ?24 lvdci_25, lvdci_dv2_25 note 3 note 3
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 7 advance product specification 1-800-255-7778 40 r lvcm os 33 (4) 22 ?2 0.4v cco - 0.4 44 ?4 66 ?6 88 ?8 12 12 ?12 16 16 ?16 24 24 ?24 lvdci_33, lvdci_dv2_33 note 3 note 3 lvttl (4) 22 ?2 0.4 2.4 44 ?4 66 ?6 88 ?8 12 12 ?12 16 16 ?16 24 24 ?24 pci33_3 note 6 note 6 0.10v cco 0.90v cco sstl18_i 6.7 ?6.7 v tt - 0.475 v tt + 0.475 sstl18_i_dci note 3 note 3 sstl2_i 7.5 ?7.5 v tt - 0.61 v tt + 0.61 sstl2_i_dci note 3 note 3 sstl2_ii 15 ?15 v tt - 0.80 v tt + 0.80 sstl2_ii_dci note 3 note 3 notes: 1. the numbers in this table are based on the conditions set forth in ta bl e 5 and table 8 . 2. descriptions of the symbols used in this table are as follows: i ol -- the output current condition under which v ol is tested i oh -- the output current condition under which v oh is tested v ol -- the output voltage that indicates a low logic level v oh -- the output voltage that indicates a high logic level v il -- the input voltage that indicates a low logic level v ih -- the input voltage that indicates a high logic level v cco -- the supply voltage for output drivers as well as lvcmos, lvttl, and pci inputs v ref -- the reference voltage for setting the input switching threshold v tt -- the voltage applied to a resistor termination 3. tested according to the standard?s relevant specifications. 4. for the lvcmos and lvttl standards: the same v ol and v oh limits apply for both the fast and slow slew attributes. 5. all dedicated output pins (cclk, done, and tdo) as well as dual-purpose totem-pole output pins (d0-d7 and busy/dout) exhibit the characteristics of lvcmos25 with 12 ma drive and fast slew rate. for information concerning the use of 3.3v signals , see the 3.3v-tolerant configuration interface section in module 2: functional description . 6. tested according to the relevant pci specifications. table 9: dc characteristics of user i/os using single-ended standards (continued) signal standard and current drive attribute (ma) test conditions logic level characteristics i ol (ma) i oh (ma) v ol max (v) v oh min (v)
spartan-3 fpga family: dc and switching characteristics 8 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r figure 1: differential input voltages ds099-3_01_012304 v inn v inp gnd level 50% v icm v icm = input common mode voltage = v id v inp internal logic differential i/o pair pins v inn n p 2 v inp + v inn v id = differential input voltage = v inp - v inn table 10: recommended operating conditions for user i/os using differential signal standards signal standard v cco (1) v id v icm v ih v il min (v) nom (v) max (v) min (mv) nom (mv) max (mv) min (v) nom (v) max (v) min (v) max (v) min (v) max (v) ldt_25 2.3752.502.62520060010000.440.600.78---- lvds_25, lvds_25_dci 2.3752.502.6251003506000.301.252.20---- blvds_25 2.3752.502.625-350--1.25----- lvdsext_25, lvdsext_25_dci 2.3752.502.62510054010000.301.202.20---- ulvds_25 2.3752.502.62520060010000.440.600.78---- lvpecl_25 2.375 2.50 2.625 100 - ----0.82.00.51.7 rsds_25 2.3752.502.625100200--1.20----- notes: 1. v cco only supplies differential output drivers, not input circuits. 2. v ref inputs are not used for any of the differential i/o standards. 3. v id is a differential measurement.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 9 advance product specification 1-800-255-7778 40 r figure 2: differential output voltages ds099-3_02_012304 v outn v outp gnd level 50% v ocm v ocm v od v ol v oh v outp internal logic v outn n p = output common mode voltage = 2 v outp + v outn v od = output differential voltage = v oh = output voltage indicating a high logic level v ol = output voltage indicating a low logic level v outp - v outn differential i/o pair pins table 11: dc characteristics of user i/os using differential signal standards signal standard device revision v od ? v od v ocm ? v ocm v oh v ol min (mv) typ (mv) max (mv) min (mv) max (mv) min (v) typ (v) max (v) min (mv) max (mv) min (v) max (v) min (v) max (v) ldt_25 all (3) 430 (4) 600 670 ?15 15 0.495 0.600 0.715 ?15 15 - - - - lvds_25 0 (3) 100 - 600 - - 0.80 - 1.6 - - - - - - future 250 - 400 - - 1.125 - 1.375 - - 1.00 1.475 0.925 1.38 blvds_25 all 250 350 450 - - - 1.20 - ---- - - lv d s e x t_ 2 5 0 (3) 100 - 600 - - 0.80 - 1.6 - - - - - - future 330 - 700 - - 1.125 - 1.375 - - - 1.700 0.705 - ulvds_25 all (3) 430 600 670 - - 0.495 0.600 0.715 - - - - - - lvpecl_25 (7) all - - - - - - - - - - 1.35 1.745 0.565 1.005 rsds_25 0 (3) 100 - 600 - - 0.80 - 1.6 - - - - - - future 100 - 400 - - 1.1 - 1.4 - - - - - - notes: 1. the numbers in this table are based on the conditions set forth in ta b l e 5 and ta b l e 1 0 . 2. v od , ? v od , and ? v ocm are differential measurements. 3. for this standard, to ensure that the fpga?s output pair meets specifications, it is necessary to set the lvdsbias option in the bitgen utility, part of the xilinx development software. see xapp 751 . the option settings for lvds_25, lvdsext_25, and rsds_25 are different from those for ldt_25 and ulvds_25. 4. this value must be compatible with the receiv er to which the fpga?s output pair is connected. 5. output voltage measurements for all differential standards are made with a termination resistor (r t ) of 100 ? across the n and p pins of the differential signal pair. 6. at any given time, only one differential standard may be assigned to each bank. 7. each lvpecl output-pair requires three external resistors: a 70 ? resistor in series with each output followed by a 240 ? shunt resistor. these are in addition to the external 100 ? termination resistor at the receiver side. see figure 3 . figure 3: external terminations for lvpecl 240 ? 70 ? 70 ? 100 ? ds099-3_08_020304
spartan-3 fpga family: dc and switching characteristics 10 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r switching characteristics all spartan-3 devices are available in two speed grades: ?4 and the higher performance ?5. switching characteristics in this document may be designated as advance, preliminary, or production. each category is defined as follows: advance : these specifications are based on simulations only and are typically available soon after establishing fpga specifications. although speed grades with this des- ignation are considered relatively stable and conservative, some under-reporting might still occur. all ?5 grade num- bers are engineering targets: characterization is still in progress. preliminary : these specifications are based on complete early silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under-reporting preliminary delays is greatly reduced compared to advance data. production : these specifications are approved once enough production silicon of a particular device family mem- ber has been characterized to provide full correlation between speed files and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typ- ically, the slowest speed grades transition to production before faster speed grades. all specified limits are representative of worst-case supply voltage and junction temperature conditions. unless other- wise noted, the following applies: parameter values apply to all spartan-3 devices. all parameters representing voltages are measured with respect to gnd. timing parameters and their representative values are selected for inclusion below either because they are impor- tant as general design requirements or they indicate funda- mental device performance characteristics. the spartan-3 speed files (v1.29), part of the xilinx development soft- ware, are the original source for many but not all of the val- ues. for more complete, more precise, and worst-case data, use the values reported by the xilinx static timing ana- lyzer (trace in the xilinx development software) and back-annotated to the simulation netlist.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 11 advance product specification 1-800-255-7778 40 r i/o timing table 12: pin-to-pin clock-to-output times for the iob output path symbol description conditions device speed grade units -5 -4 max max clock-to-output times t ickofdcm when reading from the output flip-flop (off), the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is in use. lv c m o s 2 5 (2) , 12ma output drive, fast slew rate, with dcm (3) xc3s50 2.59 ns xc3s200 2.59 ns xc3s400 2.59 ns xc3s1000 2.59 ns xc3s1500 2.60 ns xc3s2000 2.60 ns xc3s4000 2.60 ns xc3s5000 2.60 ns t ickof when reading from off, the time from the active transition on the global clock pin to data appearing at the output pin. the dcm is not in use. lv c m o s 2 5 (2) , 12ma output drive, fast slew rate, without dcm xc3s50 5.37 ns xc3s200 5.39 ns xc3s400 5.42 ns xc3s1000 5.51 ns xc3s1500 5.65 ns xc3s2000 5.83 ns xc3s4000 5.95 ns xc3s5000 6.19 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 0 and are based on the operating conditions set forth in table 5 and ta bl e 8 . 2. this clock-to-output time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or a standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. if the former is tr ue, add the appropriate input adjustment from table 16 . if the latter is true, add the appropriate output adjustment from ta bl e 1 9 . 3. dcm output jitter is included in all measurements.
spartan-3 fpga family: dc and switching characteristics 12 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 13: pin-to-pin setup and hold times for the iob input path symbol description conditions device speed grade units -5 -4 min min setup times t psdcm when writing to the input flip-flop (iff), the time from the setup of data at the input pin to the active transition at a global clock pin. the dcm is in use. lv c m o s 2 5 (2) , iobdelay = none (4) , with dcm (5) xc3s50 2.72 ns xc3s200 2.72 ns xc3s400 2.74 ns xc3s1000 2.76 ns xc3s1500 2.86 ns xc3s2000 2.98 ns xc3s4000 3.06 ns xc3s5000 3.23 ns t psfd when writing to iff, the time from the setup of data at the input pin to an active transition at the global clock pin. the dcm is not in use. lv c m o s 2 5 (2) , iobdelay = none (4) , without dcm xc3s50 2.43 ns xc3s200 3.53 ns xc3s400 3.52 ns xc3s1000 3.77 ns xc3s1500 4.15 ns xc3s2000 4.34 ns xc3s4000 4.53 ns xc3s5000 4.90 ns hold times t phdcm when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is in use. lv c m o s 2 5 (3) , iobdelay = none (4) , with dcm (5) xc3s50 ?1.81 ns xc3s200 ?1.81 ns xc3s400 ?1.81 ns xc3s1000 ?1.81 ns xc3s1500 ?1.81 ns xc3s2000 ?1.81 ns xc3s4000 ?1.80 ns xc3s5000 ?1.80 ns t phfd when writing to iff, the time from the active transition at the global clock pin to the point when data must be held at the input pin. the dcm is not in use. lv c m o s 2 5 (3) , iobdelay = none (4) , without dcm xc3s50 ?1.03 ns xc3s200 ?1.89 ns xc3s400 ?1.87 ns xc3s1000 ?2.01 ns xc3s1500 ?2.20 ns xc3s2000 ?2.20 ns xc3s4000 ?2.24 ns xc3s5000 ?2.32 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 0 and are based on the operating conditions set forth in table 5 and ta bl e 8 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or t he data input. if this is true of the global clock input, subtract the appropriate adjustment from ta b l e 1 6 . if this is true of the data input, add the appropriate input adjustment from the same table. 3. this hold time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the global clock input or th e data input. if this is true of the global clock input, add the appropriate input adjustment from table 16 . if this is true of the data input, subtract the appropriate input adjustment from the same table. when the hold time is negative, it is possible to change the data before the clock?s active edge. 4. all numbers measured with no programmed input delay. 5. dcm output jitter is included in all measurements.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 13 advance product specification 1-800-255-7778 40 r table 14: setup and hold times for the iob input path symbol description conditions device speed grade units -5 -4 min min setup times t iopick time from the setup of data at the input pin to the active transition at the iclk input of the input flip-flop (iff). no input delay is programmed. lv c m o s 2 5 (2) , iobdelay = none all 1.15 1.32 ns t iopickd time from the setup of data at the input pin to the active transition at the iff?s iclk input. the input delay is programmed. lv c m o s 2 5 (2) , iobdelay = ifd xc3s50 3.26 3.75 ns xc3s200 3.89 4.47 ns xc3s400 3.89 4.47 ns xc3s1000 4.15 4.77 ns xc3s1500 4.32 4.97 ns xc3s2000 4.50 5.17 ns xc3s4000 4.67 5.37 ns xc3s5000 5.02 5.77 ns hold times t ioickp time from the active transition at the iff?s iclk input to the point where data must be held at the input pin. no input delay is programmed. lv c m o s 2 5 (3) , iobdelay = none all ?0.66 ns t ioickpd time from the active transition at the iff?s iclk input to the point where data must be held at the input pin. the input delay is programmed. lv c m o s 2 5 (3) , iobdelay = ifd xc3s50 ?2.36 ns xc3s200 ?2.87 ns xc3s400 ?2.87 ns xc3s1000 ?3.08 ns xc3s1500 ?3.22 ns xc3s2000 ?3.36 ns xc3s4000 ?3.50 ns xc3s5000 ?3.78 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 0 and are based on the operating conditions set forth in table 5 and ta bl e 8 . 2. this setup time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. if this is true, add the appropriate input adjustment from table 16 . 3. these hold times require adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. if this is true, subtract the appropriate input adjustment from ta bl e 1 6 . when the hold time is negative, it is possible to change the data before the clock?s active edge.
spartan-3 fpga family: dc and switching characteristics 14 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 15: propagation times for the iob input path symbol description conditions device speed grade units -5 -4 max max propagation times t iopi the time it takes for data to travel from the input pin to the iob?s i output with no input delay programmed lv c m o s 2 5 (2) , iobdelay = none all 1.05 1.20 ns t iopid the time it takes for data to travel from the input pin to the i output with the input delay programmed lv c m o s 2 5 (2) , iobdelay = ifd xc3s50 3.16 3.63 ns xc3s200 3.79 4.35 ns xc3s400 3.79 4.35 ns xc3s1000 4.05 4.65 ns xc3s1500 4.22 4.85 ns xc3s2000 4.40 5.05 ns xc3s4000 4.57 5.25 ns xc3s5000 4.92 5.65 ns t iopli the time it takes for data to travel from the input pin through the iff latch to the i output with no input delay programmed lv c m o s 2 5 (2) , iobdelay = none all 1.55 1.78 ns t ioplid the time it takes for data to travel from the input pin through the iff latch to the i output with the input delay programmed lv c m o s 2 5 (2) , iobdelay = ifd xc3s50 3.66 4.21 ns xc3s200 4.29 4.93 ns xc3s400 4.29 4.93 ns xc3s1000 4.55 5.23 ns xc3s1500 4.73 5.43 ns xc3s2000 4.90 5.63 ns xc3s4000 5.07 5.83 ns xc3s5000 5.42 6.23 ns notes: 1. the numbers in this table are tested using the methodology presented in table 20 and are based on the operating conditions set forth in ta b l e 5 and ta bl e 8 . 2. this propagation time requires adjustment whenever a signal standard other than lvcmos25 is assigned to the data input. when this is true, add the appropriate input adjustment from table 16 .
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 15 advance product specification 1-800-255-7778 40 r table 16: input timing adjustments for iob convert input time from lvcmos25 to the following signal standard add the adjustment below units speed grade -5 -4 single-ended standards gtl, gtl_dci ?0.37 ?0.37 ns gtlp, gtlp_dci ?0.37 ?0.37 ns hstl_i, hstl_i_dci ?0.18 ?0.18 ns hstl_iii, hstl_iii_dci ?0.19 ?0.19 ns hstl_i_18, hstl_i_dci_18 ?0.26 ?0.26 ns hstl_ii_18, hstl_ii_dci_18 ?0.26 ?0.26 ns hstl_iii_18, hstl_iii_dci_18 ?0.20 ?0.20 ns lvcmos12 0.40 0.40 ns lvcmos15, lvdci_15, lvdci_dv2_15 0.47 0.47 ns lvcmos18, lvdci_18, lvdci_dv2_18 0.30 0.30 ns lvcmos25, lvdci_25, lvdci_dv2_25 00ns lvcmos33, lvdci_33, lvdci_dv2_33 0.09 0.09 ns lvttl ?0.31 ?0.31 ns pci33_3 0.32 0.32 ns sstl18_i, sstl18_i_dci ?0.17 ?0.17 ns sstl2_i, sstl2_i_dci ?0.19 ?0.19 ns sstl2_ii, sstl2_ii_dci ?0.21 ?0.21 ns differential standards ldt_25 0.04 0.04 ns lvds_25, lvds_25_dci 0.06 0.06 ns blvds_25 ns lvdsext_25, lvdsext_25_dci ns ulvds_25 ?0.05 ?0.05 ns lvpecl_25 ns rsds_25 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 2 0 and are based on the operating conditions set forth in ta bl e 5 , ta bl e 8 , and ta bl e 1 0 . 2. these adjustments are used to convert input path times originally specified for the lvcmos25 standard to times that correspond to other signal standards. ta b l e 1 6 : input timing adjustments for iob (continued) convert input time from lvcmos25 to the following signal standard add the adjustment below units speed grade -5 -4
spartan-3 fpga family: dc and switching characteristics 16 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 17: timing for the iob output path symbol description conditions speed grade units -5 -4 max max clock-to-output times t iockp when reading from the output flip-flop (off), the time from the active transition at the otclk input to data appearing at the output pin lv c m o s 2 5 (2) , 12ma output drive, fast slew rate 3.64 4.18 ns propagation times t ioop the time it takes for data to travel from the iob?s o input to the output pin lv c m o s 2 5 (2) , 12ma output drive, fast slew rate 2.97 3.42 ns t ioolp the time it takes for data to travel from the o input through the off latch to the output pin 3.41 3.92 ns set/reset times t iosrp time from asserting the off?s sr input to setting/resetting data at the output pin lv c m o s 2 5 (2) , 12ma output drive, fast slew rate 4.44 5.10 ns t iogsrq time from asserting the global set reset (gsr) net to setting/resetting data at the output pin 8.07 9.28 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 0 and are based on the operating conditions set forth in table 5 and ta bl e 8 . 2. this time requires adjustment whenever a signal standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from table 19 .
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 17 advance product specification 1-800-255-7778 40 r table 18: timing for the iob three-state path symbol description conditions speed grade units -5 -4 max max synchronous output enable/disable times t iockhz time from the active transition at the otclk input of the three-state flip-flop (tff) to when the output pin enters the high-impedance state lvcmos25, 12ma output drive, fast slew rate 2.32 2.66 ns t iockon (2) time from the active transition at tff?s otclk input to when the output pin drives valid data 3.78 4.34 ns asynchronous output enable/disable times t gts time from asserting the global three state net (gts) net to when the output pin enters the high-impedance state lvcmos25, 12ma output drive, fast slew rate 7.03 8.08 ns set/reset times t iosrhz time from asserting tff?s sr input to when the output pin enters a high-impedance state lvcmos25, 12ma output drive, fast slew rate 3.28 3.77 ns t iosron (2) time from asserting tff?s sr input at tff to when the output pin drives valid data 4.75 5.45 ns notes: 1. the numbers in this table are tested using the methodology presented in ta bl e 2 0 and are based on the operating conditions set forth in table 5 and ta bl e 8 . 2. this time requires adjustment whenever a signal standard other than lvcmos25 with 12 ma drive and fast slew rate is assigned to the data output. when this is true, add the appropriate output adjustment from table 19 .
spartan-3 fpga family: dc and switching characteristics 18 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 19: output timing adjustments for iob convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard add the adjustment below units speed grade -5 -4 single-ended standards gtl ?0.18 ?0.18 ns gtl_dci ?0.15 ?0.15 ns gtlp ?0.15 ?0.15 ns gtlp_dci ?0.13 ?0.13 ns hstl_i 0.08 0.08 ns hstl_i_dci 0.07 0.07 ns hstl_iii ?0.05 ?0.05 ns hstl_iii_dci ?0.05 ?0.05 ns hstl_i_18 0.14 0.14 ns hstl_i_dci_18 0 0 ns hstl_ii_18 ?0.13 ?0.13 ns hstl_ii_dci_18 0.31 0.31 ns hstl_iii_18 ?0.02 ?0.02 ns hstl_iii_dci_18 ?0.03 ?0.03 ns lvcmos12 slow 2 ma 6.47 6.47 ns 4 ma 6.70 6.70 ns 6 ma 5.60 5.60 ns fast 2 ma 3.04 3.04 ns 4 ma 2.25 2.25 ns 6 ma 2.10 2.10 ns lvcmos15 slow 2 ma 3.95 3.95 ns 4 ma 3.49 3.49 ns 6 ma 2.85 2.85 ns 8 ma 3.44 3.44 ns 12 ma 2.82 2.82 ns fast 2 ma 2.29 2.29 ns 4 ma 1.37 1.37 ns 6 ma 1.15 1.15 ns 8 ma 1.13 1.13 ns 12 ma 1.00 1.00 ns lvdci_15 1.34 1.34 ns lvdci_dv2_15 1.14 1.14 ns lvcmos18 slow 2 ma 4.31 4.31 ns 4 ma 2.69 2.69 ns 6 ma 2.23 2.23 ns 8 ma 1.83 1.83 ns 12 ma 1.97 1.97 ns 16 ma 1.62 1.62 ns fast 2 ma 2.07 2.07 ns 4 ma 0.90 0.90 ns 6 ma 0.77 0.77 ns 8 ma 0.61 0.61 ns 12 ma 0.56 0.56 ns 16 ma 0.50 0.50 ns lvdci_18 0.72 0.72 ns lvdci_dv2_18 0.58 0.58 ns lvcmos25 slow 2 ma 5.11 5.11 ns 4 ma 3.17 3.17 ns 6 ma 2.53 2.53 ns 8 ma 2.21 2.21 ns 12 ma 1.79 1.79 ns 16 ma 1.77 1.77 ns 24 ma 1.53 1.53 ns fast 2 ma 2.30 2.30 ns 4 ma 0.87 0.87 ns 6 ma 0.30 0.30 ns 8 ma 0.21 0.21 ns 12 ma 0 0 ns 16 ma 0.11 0.11 ns 24 ma 0.04 0.04 ns lvdci_25 0.19 0.19 ns lvdci_dv2_25 0.10 0.10 ns table 19: output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard add the adjustment below units speed grade -5 -4
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 19 advance product specification 1-800-255-7778 40 r lvcmos33 slow 2 ma 6.22 6.22 ns 4 ma 3.80 3.80 ns 6 ma 3.02 3.02 ns 8 ma 3.04 3.04 ns 12 ma 2.18 2.18 ns 16 ma 2.05 2.05 ns 24 ma 1.82 1.82 ns fast 2 ma 3.15 3.15 ns 4 ma 1.30 1.30 ns 6 ma 0.53 0.53 ns 8 ma 0.54 0.54 ns 12 ma 0.14 0.14 ns 16 ma 0.08 0.08 ns 24 ma ?0.03 ?0.03 ns lvdci_33 0 0 ns lvdci_dv2_33 0 0 ns lvttl slow 2 ma 6.24 6.24 ns 4 ma 3.81 3.81 ns 6 ma 3.03 3.03 ns 8 ma 3.02 3.02 ns 12 ma 2.17 2.17 ns 16 ma 2.05 2.05 ns 24 ma 1.88 1.88 ns fast 2 ma 3.14 3.14 ns 4 ma 1.31 1.31 ns 6 ma 0.50 0.50 ns 8 ma 0.51 0.51 ns 12 ma 0.12 0.12 ns 16 ma 0.06 0.06 ns 24 ma 0 0 ns table 19: output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard add the adjustment below units speed grade -5 -4 pci33_3 ?0.26 ?0.26 ns sstl18_i ?0.05 ?0.05 ns sstl18_i_dci ?0.01 ?0.01 ns sstl2_i 0.08 0.08 ns sstl2_i_dci 0.01 0.01 ns sstl2_ii ?0.04 ?0.04 ns sstl2_ii_dci ?0.14 ?0.14 ns differential standards ldt_25 ?0.52 ?0.52 ns lvds_25 ?0.50 ?0.50 ns lvds_25_dci ns blvds_25 ?0.01 ?0.01 ns lvdsext_25 ?0.50 ?0.50 ns lvdsext_25_dci ns ulvds_25 ?0.48 ?0.48 ns lvpecl_25 ns rsds_25 ns notes: 1. the numbers in this table are tested using the methodology presented in ta b l e 2 0 and are based on the operating conditions set forth in ta bl e 5 , ta bl e 8 , and ta bl e 1 0 . 2. these adjustments are used to convert output- and three-state-path times originally specified for the lvcmos25 standard with 12 ma drive and fast slew rate to times that correspond to other signal standards. do not adjust times that measure when outputs go into a high-impedance state. table 19: output timing adjustments for iob (continued) convert output time from lvcmos25 with 12ma drive and fast slew rate to the following signal standard add the adjustment below units speed grade -5 -4
spartan-3 fpga family: dc and switching characteristics 20 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r timing measurement methodology when measuring timing parameters at the programmable i/os, different signal standards call for different test condi- tions. ta b l e 2 0 presents the conditions to use for each stan- dard. the method for measuring input timing is as follows: a sig- nal that swings between a low logic level of v l and a high logic level of v h is applied to the input under test. some standards also require the application of a bias voltage to the v ref pins of a given bank to properly set the input-switching threshold. the measurement point of the input signal (v m ) is commonly located halfway between v l and v h . the output test setup is shown in figure 4 . a termination voltage v t is applied to the termination resistor r t , the other end of which is connected to the output. for each standard, r t and v t generally take on the standard values recom- mended for minimizing signal reflections. if the standard does not ordinarily use terminations (e.g., lvcmos, lvttl), then r t is set to 1m ? to indicate an open connec- tion, and v t is set to zero. the same measurement point (v m ) that was used at the input is also used at the output. figure 4: output test setup fpga output v t (v ref ) r t (r ref ) v m (v meas ) c l (c ref ) ds099-3_07_012004 notes: 1. the names shown in parentheses are used in the ibis file. table 20: test methods for timing measurement at i/os signal standard inputs outputs inputs and outputs v ref (v) v l (v) v h (v) r t ( ? ) v t (v) v m (v) single-ended gtl 0.8 v ref - 0.2 v ref + 0.2 25 1.2 v ref gtl_dci 50 1.2 gtlp 1.0 v ref - 0.2 v ref + 0.2 25 1.5 v ref gtlp_dci 50 1.5 hstl_i 0.75 v ref - 0.5 v ref + 0.5 50 0.75 v ref hstl_i_dci 50 0.75 hstl_iii 0.90 v ref - 0.5 v ref + 0.5 50 1.5 v ref hstl_iii_dci 50 1.5 hstl_i_18 0.90 v ref - 0.5 v ref + 0.5 50 0.9 v ref hstl_i_dci_18 50 0.9 hstl_ii_18 0.90 v ref - 0.5 v ref + 0.5 25 0.9 v ref hstl_ii_dci_18 50 0.9 hstl_iii_18 1.1 v ref - 0.5 v ref + 0.5 50 1.8 v ref hstl_iii_dci_18 50 1.8 lvcm os 12 - 0 1 .2 1m 0 lvcmos15 - 0 1.5 1m 0 0.75 lvdci_15 1m 0 lvdci_dv2_15 1m 0
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 21 advance product specification 1-800-255-7778 40 r lvcmos18 - 0 1.8 1m 0 0.9 lvdci_18 1m 0 lvdci_dv2_18 1m 0 lvcmos25 - 0 2.5 1m 0 1.25 lvdci_25 1m 0 lvdci_dv2_25 1m 0 lvcmos33 - 0 3.3 1m 0 1.65 lvdci_33 1m 0 lvdci_dv2_33 1m 0 lvttl - 0 3.3 1m 0 1.4 pci33_3 rising - note 2 note 2 25 0 0.94 falling 25 3.3 2.03 sstl18_i 0.9 v ref - 0.5 v ref + 0.5 50 0.9 v ref sstl18_i_dci 50 0.9 sstl2_i 1.25 v ref - 0.75 v ref + 0.75 50 1.25 v ref sstl2_i_dci 50 1.25 sstl2_ii 1.25 v ref - 0.75 v ref + 0.75 25 1.25 v ref sstl2_ii_dci 50 1.25 differential ldt_25 - 0.6 - 0.125 0.6 + 0.125 60 0.6 0.6 lvds_25 - 1.2 - 0.125 1.2 + 0.125 50 1.2 1.2 lvds_25_dci 1m 0 blvds_25 - 1.2 - 0.125 1.2 + 0.125 1m 0 1.2 lvdsext_25 - 1.2 - 0.125 1.2 + 0.125 50 1.2 1.2 lvdsext_25_dci - - ulvds_25 - 0.6 - 0.125 0.6 + 0.125 60 0.6 0.6 lvpecl_25 - 1.6 - 0.3 1.6 + 0.3 1m 0 1.6 rsds_25 - 1.3 - 0.1 1.3 + 0.1 50 1.2 1.2 notes: 1. descriptions of the relevant symbols are as follows: v ref -- the reference voltage for setting the input switching threshold v m -- voltage of measurement point on signal transition v l -- low-level test voltage at input pin v h -- high-level test voltage at input pin r t -- effective termination resistance, which takes on a value of 1m ? when no parallel termination is required v t -- termination voltage c l -- load capacitance at output pin, which is 0 pf for all standards 2. according to the pci specification. table 20: test methods for timing measurement at i/os (continued) signal standard inputs outputs inputs and outputs v ref (v) v l (v) v h (v) r t ( ? ) v t (v) v m (v)
spartan-3 fpga family: dc and switching characteristics 22 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r the capacitive load (c l ) is connected between the output and gnd. the output timing for all standards, as published in the speed files and the data sheet, is always based on a c l value of zero unless otherwise specified. high-imped- ance probes (less than 1 pf) are used for all measure- ments. any delay that the test fixture might contribute to test measurements is subtracted from those measurements to produce the final timing numbers as published in the speed files and data sheet. using ibis models to simulate load conditions in application ibis models permit the most accurate prediction of timing delays for a given application. the parameters found in the ibis model (v ref , r ref , c ref , and v meas ) correspond directly with the parameters used in ta b l e 2 0 , v t , r t , c l , and v m . do not confuse v ref (the termination voltage) from the ibis model with v ref (the input-switching threshold) from the table! the four parameters describe all relevant output test conditions. ibis models are found at the following link: http://www.xilinx.com/support/sw_ibis.htm simulate delays for a given application according to its spe- cific load conditions as follows: 1. simulate the desired signal standard with the output driver connected to the test setup shown in figure 4 . use parameter values v t , r t , c l , and v m from ta b l e 2 0 . 2. record the time to v m . 3. simulate the same signal standard with the output driver connected to the pcb trace with load. use the appropriate ibis model (including v ref , r ref , c ref , and v meas values) or capacitive value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase (or decrease) in delay should be added to (or subtracted from) the appropriate output standard adjustment ( ta b l e 1 9 ) to yield the worst-case delay of the pcb trace. simultaneously switching output guidelines table 21: equivalent v cco /gnd pairs per bank device vq100 tq144 pq208 ft256 fg320 fg456 fg676 fg900 fg1156 xc3s50112------ xc3s2001123----- xc3s400- 12335 - - - xc3s1000- - 23355 - - xc3s1500----356-- xc3s2000------69- xc3s4000-------1012 xc3s5000-------1012
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 23 advance product specification 1-800-255-7778 40 r table 22: maximum number of simultaneously switching outputs per v cco -gnd pair signal standard package vq100, tq144, pq208 ft256, fg320, fg456, fg676, fg900, fg1156 single-ended standards gtl 4 gtlp_dci 3 gtlp 4 gtlp_dci 3 hstl_i 17 hstl_i_dci 17 hstl_iii 7 hstl_iii_dci 7 hstl_i_18 17 hstl_i_dci_18 hstl_ii_18 9 hstl_ii_dci_18 hstl_iii_18 8 hstl_iii_dci_18 lv c m o s 1 2 s l ow 2 5 5 432 618 fast 2 31 413 69 lv c m o s 1 5 s l ow 2 5 5 431 618 815 12 10 fast 2 25 416 613 811 12 7 lvdci_15 10 lvdci_dv2_15 5 lv c m o s 1 8 s l ow 2 6 4 434 622 818 12 13 16 10 fast 2 36 421 613 810 12 9 16 6 lvdci_18 11 lvdci_dv2_18 6 lv c m o s 2 5 s l ow 2 7 6 446 633 824 12 18 16 11 24 7 fast 2 42 420 615 813 12 11 16 8 24 5 lvdci_25 13 lvdci_dv2_25 7 table 22: maximum number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard package vq100, tq144, pq208 ft256, fg320, fg456, fg676, fg900, fg1156
spartan-3 fpga family: dc and switching characteristics 24 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r lv c m o s 3 3 (1) slow 2 76 446 627 820 12 13 16 10 24 9 fast 2 44 426 616 812 12 10 16 7 24 3 lvdci_33 (1) 13 lvdci_dv2_33 (1) 7 lv t t l (1) slow 2 60 441 629 822 12 13 16 11 24 9 fast 2 34 420 615 812 12 10 16 9 24 5 table 22: maximum number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard package vq100, tq144, pq208 ft256, fg320, fg456, fg676, fg900, fg1156 pci33_3 (1) sstl18_i 17 sstl18_i_dci sstl2_i 13 sstl2_i_dci 15 sstl2_ii 9 sstl2_ii_dci 5 differential standards ldt_25 lv d s _ 2 5 lvds_25_dci blvds_25 lvdsext_25 lvdsext_25_dci ulvds_25 lv p e c l _ 2 5 rsds_25 notes: 1. the numbers in this table are recommendations that assume sound board layout practice. for cases that exceed these maximum numbers, perform ibis simulations to confirm signal integrity. table 22: maximum number of simultaneously switching outputs per v cco -gnd pair (continued) signal standard package vq100, tq144, pq208 ft256, fg320, fg456, fg676, fg900, fg1156
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 25 advance product specification 1-800-255-7778 40 r core logic timing table 23: clb timing symbol description speed grade units -5 -4 min max min max clock-to-output times t cko when reading from the ffx (ffy) flip-flop, the time from the active transition at the clk input to data appearing at the xq (yq) output - 0.67 - 0.77 ns setup times t dy ck time from the setup of data at the d input to the active transition at the clk input of ffx 0.08 - 0.09 - ns t dxck time from the setup of data at the d input to the active transition at the clk input of ffy 0.08 - 0.09 - ns hold times t ckdy time from the active transition at ffy?s clk input to the point where data is last held at the d input 0.01 - 0.01 - ns t ckdx time from the active transition at ffx?s clk input to the point where data is last held at the d input 0.01 - 0.01 - ns clock timing t ch the high pulse width of the clb?s clk signal 0.76 - 0.87 - ns t cl the low pulse width of the clk signal 0.76 - 0.87 - ns f tog maximum toggle frequency (for export control) - 500 - 500 mhz propagation times t ilo the time it takes for data to travel from the clb?s f (g) input to input to the x (y) output - 0.65 - 0.75 ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 .
spartan-3 fpga family: dc and switching characteristics 26 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r table 24: synchronous 18 x 18 multiplier timing symbol description p outputs speed grade units -5 -4 minmaxminmax clock-to-output times t multck when reading from the multiplier, the time from the active transition at the c clock input to data appearing at the p outputs p[0] - 0.76 - 0.88 ns p[15] - 0.97 - 1.11 ns p[17] - 1.17 - 1.34 ns p[19] - 1.37 - 1.58 ns p[23] - 1.78 - 2.04 ns p[31] - 2.59 - 2.97 ns p[35] - 3.00 - 3.44 ns setup times t mulidck time from the setup of data at the a and b inputs to the active transition at the c input of the multiplier -2.18-2.50- ns hold times t mulckid time from the active transition at the multiplier?s c input to the point where data is last held at the a and b inputs -0-0-ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 . table 25: asynchronous 18 x 18 multiplier timing symbol description p outputs speed grade units -5 -4 max max propagation times t mult the time it takes for data to travel from the a and b inputs to the p outputs p[0] 1.25 1.44 ns p[15] 2.88 3.31 ns p[17] 3.10 3.56 ns p[19] 3.32 3.81 ns p[23] 3.75 4.31 ns p[31] 4.62 5.31 ns p[35] 5.06 5.81 ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 .
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 27 advance product specification 1-800-255-7778 40 r table 26: block ram timing symbol description speed grade units -5 -4 min max min max clock-to-output times t bcko when reading from the block ram, the time from the active transition at the clk input to data appearing at the dout output - 2.10 - 2.41 ns setup times t bdck time from the setup of data at the din inputs to the active transition at the clk input of the block ram 0.43 - 0.49 - ns hold times t bckd time from the active transition at the block ram?s clk input to the point where data is last held at the din inputs 0-0-ns clock timing t bpwh the high pulse width of the block ram?s clk signal 1.26 - 1.44 - ns t bpwl the low pulse width of the clk signal 1.26 - 1.44 - ns notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 .
spartan-3 fpga family: dc and switching characteristics 28 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r digital clock manager (dcm) timing for specification purposes, the dcm consists of three key components: the delay-locked loop (dll), the digital fre- quency synthesizer (dfs), and the phase shifter (ps). aspects of dll operation play a role in all dcm applica- tions. all such applications inevitably use the clkin and the clkfb inputs connected to either the clk0 or the clk2x feedback, respectively. thus, specifications in the dll tables ( ta bl e 2 7 and ta b l e 2 8 ) apply to any application that only employs the dll component. when the dfs and/or the ps components are used together with the dll, then the specifications listed in the dfs and ps tables ( ta b l e 2 9 through ta b l e 3 2 ) supersede any corresponding ones in the dll tables. dll specifications that do not change with the addition of dfs or ps functions are presented in ta b l e 2 7 and ta b l e 2 8 . table 27: recommended operating conditions for the dll symbol description frequency mode/ f clkin range device revision speed grade units -5 -4 min max min max input frequency ranges f clkin clkin_freq_dll_lf frequency for the clkin input low all 24 (2) 165 (3) 24 165 (3) mhz clkin_freq_dll_hf high 0 48 280 (3) 48 280 (3) mhz future 48 326 48 tbd mhz input pulse requirements clkin_pulse clkin pulse width as a percentage of the clkin period all 0 45% 55% 45% 55% - f clkin < 200 mhz future 40% 60% 40% 60% - f clkin > 200 mhz 45% 55% 45% 55% - input clock jitter and delay path variation clkin_cyc_jitt_dll_lf cycle-to-cycle jitter at the clkin input low all -300 +300 -300 +300 ps clkin_cyc_jitt_dll_hf high -150 +150 -150 +150 ps clkin_cyc_per_dll_lf period jitter at the clkin input low -1 +1 -1 +1 ns clkin_cyc_per_dll_hf high -1 +1 -1 +1 ns clkfb_delay_var_ext allowable variation of off-chip feedback delay from the dcm output to the clkfb input all -1 +1 -1 +1 ns notes: 1. dll specifications apply when any of the dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. 2. use of the dfs permits lower f clkin frequencies. see ta b l e 2 9 . 3. to double the maximum effective f clkin limit, set the clkin_divide_by_2 attribute to true.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 29 advance product specification 1-800-255-7778 40 r table 28: switching characteristics for the dll symbol description frequency mode / f clkin range device revision speed grade units -5 -4 minmaxminmax output frequency ranges clkout_freq_1x_lf frequency for the clk0, clk90, clk180, and clk270 outputs low all 24 165 24 165 mhz clkout_freq_1x_hf frequency for the clk0 and clk180 outputs high 0 no phase shifting 48 280 48 280 mhz phase shifting 48 200 48 200 mhz future 48 326 48 tbd mhz clkout_freq_2x_lf frequency for the clk2x and clk2x180 outputs low 0 (3) 48 330 48 330 mhz future 48 330 48 330 mhz clkout_freq_dv_lf frequency for the clkdv output low all 1.5 100 1.5 100 mhz clkout_freq_dv_hf high all 3 215 3 215 mhz output clock jitter clkout_per_jitt_0 period jitter at the clk0 output all all -100 +100 -100 +100 ps clkout_per_jitt_90 period jitter at the clk90 output -150 +150 -150 +150 ps clkout_per_jitt_180 period jitter at the clk180 output -150 +150 -150 +150 ps clkout_per_jitt_270 period jitter at the clk270 output -150 +150 -150 +150 ps clkout_per_jitt_2x period jitter at the clk2x and clk2x180 outputs -200 +200 -200 +200 ps clkout_per_jitt_dv1 period jitter at the clkdv output when performing integer division -150 +150 -150 +150 ps clkout_per_jitt_dv2 period jitter at the clkdv output when performing non-integer division -300 +300 -300 +300 ps duty cycle clkout_duty_cycle_dll (4) duty cycle variation for the clk0, clk90, clk180, clk270, clk2x, clk2x180, and clkdv outputs all all -150 +150 -150 +150 ps
spartan-3 fpga family: dc and switching characteristics 30 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r phase alignment clkin_clkfb_phase phase offset between the clkin and clkfb inputs all all -50 +50 -50 +50 ps clkout_phase phase offset between any dll output and any other dcm outputs all all -140 +140 -140 +140 ps lock time lock_dll_24_30 time required to achieve lock 24 mhz < f clkin < 30 mhz all - 960 - 960 s lock_dll_30_40 30 mhz < f clkin < 40 mhz - 720 - 720 s lock_dll_40_50 40 mhz < f clkin < 50 mhz - 400 - 400 s lock_dll_50_60 50 mhz < f clkin < 60 mhz - 200 - 200 s lock_dll_60 f clkin > 60 mhz - 160 - 160 s delay lines dcm_tap delay tap resolution all all 30.0 60.0 30.0 60.0 ps notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 and ta bl e 2 7 . 2. dll specifications apply when any of the dll outputs (clk0, clk90, clk180, clk270, clk2x, clk2x180, or clkdv) are in use. 3. for rev. 0 devices only, use feedback from the clk0 output (instead of the clk2x output) and set the clk_feedback attribute to 1x . 4. this specification only applies if the attribute duty_cycle_correction = true. table 28: switching characteristics for the dll (continued) symbol description frequency mode / f clkin range device revision speed grade units -5 -4 minmaxminmax
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 31 advance product specification 1-800-255-7778 40 r table 29: recommended operating conditions for the dfs symbol description frequency mode speed grade units -5 -4 min max min max input frequency ranges (2) f clkin clk_freq_fx frequency for the clkin input low 1 210 1 210 mhz clk_freq_fx_hf high 48 280 48 280 mhz input clock jitter clkin_cyc_jitt_fx_lf cycle-to-cycle jitter at the clkin input low -300 +300 -300 +300 ps clkin_cyc_jitt_fx_hf high -150 +150 -150 +150 ps clkin_cyc_per_fx_lf period jitter at the clkin input low -1+1-1+1ns clkin_cyc_per_fx_hf high -1 +1 -1 +1 ns notes: 1. dfs specifications apply when either of the dfs outputs (clkfx or clkfx180) are in use. 2. if both dfs and dll outputs are used on the same dcm, follow the more restrictive clkin_freq_dll specifications in ta bl e 2 7 . table 30: switching characteristics for the dfs symbol description frequency mode device revision speed grade units -5 -4 min max min max output frequency ranges clkout_freq_fx_lf frequency for the clkfx and clkfx180 outputs low all 24 210 24 210 mhz clkout_freq_fx_hf high 0 210 280 210 280 mhz future 210 326 210 tbd mhz output clock jitter clkout_per_jitt_fx period jitter at the clkfx and clkfx180 outputs all all ps duty cycle (3) clkout_duty_cycle_fx duty cycle precision for the clkfx and clkfx180 outputs all all -100 +100 -100 +100 ps phase alignment clkout_phase phase offset between either dfs output and any other dcm output all all -140 +140 -140 +140 ps lock time lock_fx once the clkin and clkfb signals become in-phase, the time it takes for the dcm?s locked output to go high. all all - 10.0 - 10.0 ms notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 and ta bl e 2 9 . 2. dfs specifications apply when either of the dfs outputs (clkfx or clkfx180) is in use. 3. the clkfx and clkfx180 outputs always approximate 50% duty cycles.
spartan-3 fpga family: dc and switching characteristics 32 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r phase shifter (ps) phase shifter operation is only supported in the low fre- quency mode. for rev. 0 devices, the variable phase mode only permits positive shifts. for any desired negative phase shift (?s), an equivalent positive phase shift (360 ? s) is possible. in order to use the variable phase mode, it is nec- essary to set the bitgen option centered_x#y# option to 0. bitgen is part of the xilinx development software. the lines to be typed in the command prompt are shown in ta bl e 3 3 , page 33 . table 31: recommended operating conditions for the ps in variable phase mode symbol description frequency mode/ f psclk range device revision speed grade units -5 -4 min max min max operating frequency ranges psclk_freq (f psclk ) frequency for the psclk input low all 1 165 1 165 mhz input pulse and requirements psclk_pulse psclk pulse width as a percentage of the psclk period low 0 45% 55% 45% 55% - low f psclk < 200 mhz future 40% 60% 40% 60% - f psclk > 200 mhz 45% 55% 45% 55% - notes: 1. the ps specifications in this table apply when the ps attribute clkout_phase_shift= variable. table 32: switching characteristics for the ps in variable phase mode symbol description frequency mode speed grade units -5 -4 min max min max phase shifting range fine_shift_range range for variable phase shifting low - 10.0 - 10.0 ns lock time lock_dll_fine_shift (3) in the variable phase mode, the additional time it takes for the dcm?s locked output to go high low --ms notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 and table 31 . 2. the ps specifications in this table apply when the ps attribute clkout_phase_shift= variable. 3. when in the variable phase mode, add the values for this parameter to the appropriate lock_dll parameter from ta bl e 2 8 for the total lock time.
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 33 advance product specification 1-800-255-7778 40 r table 33: bitgen commands for variable phase mode device dcm location (device top view) bitgen command line xc3s50 upper bitgen -g centered_x0y1:0 design_name .ncd lower bitgen -g centered_x0y0:0 design_name .ncd all others upper left bitgen -g centered_x0y1:0 design_name .ncd upper right bitgen -g centered_x1y1:0 design_name .ncd lower left bitgen -g centered_x0y0:0 design_name .ncd lower right bitgen -g centered_x1y0:0 design_name .ncd
spartan-3 fpga family: dc and switching characteristics 34 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r configuration and jtag timing figure 5: waveforms for power-on and the beginning of configuration table 34: power-on timing and the beginning of configuration symbol description device all speed grades units min max t por (2) the time from the application of v ccint , v ccaux , and v cco bank 4 supply voltages (whichever occurs last) to the rising transition of the init_b pin xc3s50 - 5 ms xc3s200 - 5 ms xc3s400 - 5 ms xc3s1000 - 5 ms xc3s1500 - 7 ms xc3s2000 - 7 ms xc3s4000 - 7 ms xc3s5000 - 7 ms t prog the width of the low-going pulse on the prog_b pin all 0.3 - s t pl (2) the time from the rising edge of the prog_b pin to the rising transition on the init_b pin xc3s50 - 2 ms xc3s200 - 2 ms xc3s400 - 2 ms xc3s1000 - 2 ms xc3s1500 - 3 ms xc3s2000 - 3 ms xc3s4000 - 3 ms xc3s5000 - 3 ms t icck (3) the time from the rising edge of the init_b pin to the generation of the configuration clock signal at the cclk output pin all 0.5 4.0 s notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 . 2. power-on reset and the clearing of configuration memory occurs during this period. 3. this specification applies only for the master serial and master parallel modes. v ccint (supply) (supply) (supply) v ccaux v cco bank 4 prog_b (output) (open-drain) (input) init_b cclk ds099-3_03_022904 1.2v 2.5v 2.5v t icck t prog t pl t por notes: 1. the v ccint , v ccaux , and v cco supplies may be applied in any order. 2. the low-going pulse on prog_b is optional after power-on but necessary for reconfiguration without a power cycle. 3. the rising edge of init_b samples the voltage levels applied to the mode pins (m0 - m2).
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 35 advance product specification 1-800-255-7778 40 r figure 6: waveforms for master and slave serial configuration ds099-3_04_041103 bit 0 bit 1 bit n bit n+1 bit n-64 bit n-63 1/f ccser t cch t dcc t ccd t ccl t cco prog_b (input) din (input) dout (output) (open-drain) init_b (input/output) cclk notes: 1. the cs_b, write_b, and busy signals are not used in the serial modes. keep the cs_b and write_b inputs inactive (i.e., both pins high). table 35: timing for the master and slav e serial configuration modes symbol description slave/master all speed grades units min max clock-to-output times t cco the time from the rising transition on the cclk pin to data appearing at the dout pin both - 12.0 ns setup times t dcc the time from the setup of data at the din pin to the rising transition at the cclk pin both - 10.0 ns hold times t ccd the time from the rising transition at the cclk pin to the point when data is last held at the din pin both - 0 ns clock timing t cch the high pulse width at the cclk input pin slave 5.0 - ns t ccl the low pulse width at the cclk input pin 5.0 - ns f ccser frequency of the clock signal at the cclk input pin -66mhz ? f ccser variation from the generated cclk frequency set using the configrate bitgen option master ?50% +50% - notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 .
spartan-3 fpga family: dc and switching characteristics 36 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r figure 7: waveforms for master and slave parallel configuration ds099-3_05_041103 byte 0 byte 1 byte n busy high-z high-z byte n+1 t smwcc 1/f ccpar t smcccs t ccl t smckby t smckby t cch t smccw t smccd t smcscc t smdcc prog_b (input) (open-drain) init_b (input) cs_b (output) busy rdwr_b (input) (input/output) cclk (inputs) d0 - d7 notes: 1. switching rdwr_b high or low while holding cs_b low asynchronously aborts configuration. table 36: timing for the master and slave parallel configuration modes symbol description slave/master all speed grades units min max clock-to-output times t smckby the time from the rising transition on the cclk pin to a signal transition at the busy pin slave - 12.0 ns setup times t smdcc the time from the setup of data at the d0-d7 pins to the rising transition at the cclk pin both 10.0 - ns t smcscc the time from the setup of a logic level at the cs_b pin to the rising transition at the cclk pin 10.0 - ns t smccw (2) the time from the setup of a logic level at the rdwr_b pin to the rising transition at the cclk pin 10.0 - ns
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 37 advance product specification 1-800-255-7778 40 r hold times t smccd the time from the rising transition at the cclk pin to the point when data is last held at the d0-d7 pins both 0 - ns t smcccs the time from the rising transition at the cclk pin to the point when a logic level is last held at the cs_b pin 0-ns t smwcc (2) the time from the rising transition at the cclk pin to the point when a logic level is last held at the rdwr_b pin 0-ns clock timing t cch the high pulse width at the cclk input pin slave 5 - ns t ccl the low pulse width at the cclk input pin 5 - ns f ccpar frequency of the clock signal at the cclk input pin not using the busy pin (3) -66mhz using the busy pin - 100 mhz ? f ccpar variation from the generated cclk frequency set using the bitgen option configrate master ?50% +50% - notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 . 2. rdwr_b is synchronized to cclk for the purpose of performing the abort operation. the same pin asynchronously controls the driver impedance of the d0 - d7 pins. to avoid contention when writing configuration data to the d0 - d7 bus, do not bring rdwr _b high when cs_b is low. 3. in the slave parallel mode, it is necessary to use the busy pin when the cclk frequency exceeds this maximum specification. table 36: timing for the master and slave parallel configuration modes (continued) symbol description slave/master all speed grades units min max
spartan-3 fpga family: dc and switching characteristics 38 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r figure 8: jtag waveforms tck t tmstck tms tdi tdo (input) (input) (input) (output) t tcktms t tcktdi t tcktdo t tditck ds099_06_040703 t cch t ccl 1/f tck table 37: timing for the jtag test access port symbol description all speed grades units min max clock-to-output times t tcktdo the time from the falling transition on the tck pin to data appearing at the tdo pin -11.0ns setup times t tditck the time from the setup of data at the tdi pin to the rising transition at the tck pin 5.0 - ns t tmstck the time from the setup of a logic level at the tms pin to the rising transition at the tck pin 5.0 - ns hold times t tcktdi the time from the rising transition at the tck pin to the point when data is last held at the tdi pin 0-ns t tcktms the time from the rising transition at the tck pin to the point when a logic level is last held at the tms pin 0-ns clock timing t cch the high pulse width at the tck pin 5 - ns t ccl the low pulse width at the tck pin 5 - ns f tck frequency of the tck signal - 33 mhz notes: 1. the numbers in this table are based on the operating conditions set forth in ta bl e 5 .
spartan-3 fpga family: dc and switching characteristics ds099-3 (v1.3) march 4, 2004 www.xilinx.com 39 advance product specification 1-800-255-7778 40 r revision history the spartan-3 family data sheet ds099-1 , spartan-3 fpga family: introduction and ordering information (module 1) ds099-2, spartan-3 fpga family: functional description (module 2) ds099-3, spartan-3 fpga family: dc and switching characteristics (module 3) ds099-4 , spartan-3 fpga family: pinout descriptions (module 4) date version no. description 04/11/03 1.0 initial xilinx release. 07/11/03 1.1 extended absolute maximum rating for junction temperature in ta b l e 1 . added numbers for typical quiescent supply current ( ta b l e 7 ) and dll timing. 02/06/04 1.2 revised v in maximum rating ( ta b l e 1 ). added power-on requirements ( ta b l e 3 ), leakage current number ( ta bl e 6 ), and differential output voltage levels ( ta b l e 1 1 ) for rev. 0. published new quiescent current numbers ( ta b l e 7 ). updated pull-up and pull-down resistor strengths ( ta b l e 6 ). added lvdci_dv2 and lvpecl standards ( ta b l e 1 0 and ta b l e 1 1 ). changed cclk setup time ( ta b l e 3 5 and ta bl e 3 6 ). 03/04/04 1.3 added timing numbers from v1.29 speed files as well as dcm timing ( ta bl e 2 7 through ta bl e 3 2 ).
spartan-3 fpga family: dc and switching characteristics 40 www.xilinx.com ds099-3 (v1.3) march 4, 2004 1-800-255-7778 advance product specification r
ds099-4 (v1.5) july 13, 2004 www.xilinx.com 1 preliminary product spec ification 1-800-255-7778 ? 2003-2004 xilinx, inc. all rights reserved. all xilinx trademark s, registered trademarks, patents, and disclaimers are as lis ted at http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. introduction this data sheet module describes the various pins on a spartan?-3 fpga and how they connect to the supported component packages. the pin types section categorizes all of the fpga pins by their function type. the pin definitions section provides a top-level description for each pin on the device. the detailed, functional pin descriptions section offers significantly more detail about each pin, especially for the dual- or special-function pins used during device configuration. some pins have associated optional behavior, controlled by settings in the configuration bitstream. these options are described in the bitstream options section. the package overview section describes the various packaging options available for spartan-3 fpgas. detailed pin list tables and footprint diagrams are provided for each package solution. pin descriptions pin types a majority of the pins on a spartan-3 fpga are gen- eral-purpose, user-defined i/o pins. there are, however, up to 12 different functional types of pins on spartan-3 pack- ages, as outlined in ta bl e 1 . in the package footprint draw- ings that follow, the individual pins are color-coded according to pin type as in the table. 0105 spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 00 product specification r ta bl e 1 : types of pins on spartan-3 fpgas type/ color code description pin name(s) in type i/o unrestricted, general-purpose user-i/o pin. most pins can be paired together to form differential i/os. io, io_lxxy_# dual dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user i/o after configuration. if the pin is not used during configuration, this pin behaves as an i/o-type pin. there are 12 dual-purpose configuration pins on every package. io_lxxy_#/din/d0, io_lxxy_#/d1, io_lxxy_#/d2, io_lxxy_#/d3, io_lxxy_#/d4, io_lxxy_#/d5, io_lxxy_#/d6, io_lxxy_#/d7, io_lxxy_#/cs_b, io_lxxy_#/rdwr_b, io_lxxy_#/busy/dout, io_lxxy_#/init_b config dedicated configuration pin. not available as a user-i/o pin. every package has seven dedicated configuration pins. these pins are powered by vccaux. cclk, done, m2, m1, m0, prog_b, hswap_en jtag dedicated jtag pin. not available as a user-i/o pin. every package has four dedicated jtag pins. these pins are powered by vccaux. tdi, tms, tck, tdo dci dual-purpose pin that is either a user-i/o pin or used to calibrate output buffer impedance for a specific bank using digital controlled impedance (dci). there are two dci pins per i/o bank. io/vrn_# io_lxxy_#/vrn_# io/vrp_# io_lxxy_#/vrp_# vref dual-purpose pin that is either a user-i/o pin or, along with all other vref pins in the same bank, provides a reference voltage input for certain i/o standards. if used for a reference voltage within a bank, all vref pins within the bank must be connected. io/vref_# io_lxxy_#/vref_#
spartan-3 fpga family: pinout descriptions 2 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r i/os with lxxy_# are part of a differential output pair. ?l? indi- cates differential output cap ability. the ?xx? field is a two-digit integer, unique to each bank that identifies a differ- ential pin-pair. the ?y? field is either ?p? for the true signal or ?n? for the inverted signal in the differential pair. the ?#? field is the i/o bank number. pin definitions ta b l e 2 provides a brief description of each pin listed in the spartan-3 pinout tables and package footprint diagrams. pins are categorized by their pin type, as listed in ta b l e 1 . see detailed, functional pin descriptions for more infor- mation. gnd dedicated ground pin. the number of gnd pins depends on the package used. all must be connected. gnd vccaux dedicated auxiliary power supply pin. the number of vccaux pins depends on the package used. all must be connected to +2.5v. vccaux vccint dedicated internal core logic power supply pin. the number of vccint pins depends on the package used. all must be connected to +1.2v. vccint vcco dedicated i/o bank, output buffer power supply pin. along with other vcco pins in the same bank, this pin supplies power to the output buffers within the i/o bank and sets the input threshold voltage for some i/o standards. vcco_# tq144 package only: vcco_left, vcco_top, vcco_right, vcco_bottom gclk dual-purpose pin that is either a user-i/o pin or an input to a specific global buffer input. every package has eight dedicated gclk pins. io_lxxy_#/gclk0, io_lxxy_#/gclk1, io_lxxy_#/gclk2, io_lxxy_#/gclk3, io_lxxy_#/gclk4, io_lxxy_#/gclk5, io_lxxy_#/gclk6, io_lxxy_#/gclk7 n.c. this package pin is not connected in this specific device/package combination but may be connected in larger devices in the same package. n.c. notes: 1. # = i/o bank number, an integer between 0 and 7. ta bl e 1 : types of pins on spartan-3 fpgas (continued) type/ color code description pin name(s) in type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 3 product specification 1-800-255-7778 r ta bl e 2 : spartan-3 pin definitions pin name direction description i/o: general-purpose i/o pins i/o user-defined as input, output, bidirectional, three-state output, open-drain output, open-source output user i/o: unrestricted single-ended user-i/o pin. supports all i/o standards except the differential standards. i/o_lxxy_# user-defined as input, output, bidirectional, three-state output, open-drain output, open-source output user i/o, half of differential pair: unrestricted single-ended user-i/o pin or half of a differential pair. supports all i/o standards including the differential standards. dual: dual-purpose configuration pins io_lxxy_#/din/d0, io_lxxy_#/d1, io_lxxy_#/d2, io_lxxy_#/d3, io_lxxy_#/d4, io_lxxy_#/d5, io_lxxy_#/d6, io_lxxy_#/d7 input during configuration possible bidirectional i/o after configuration if selectmap port is retained. otherwise, user i/o after configuration configuration data port: in parallel (selectmap) modes, d0 -d7 are byte-wide configuration data pins. these pins become user i/os after configuration unless the selectmap port is retained via the persist bitstream option. in serial modes, din (d0) serves as the single configuration data input. this pin becomes a user i/o after configuration unless retained by the persist bitstream option. io_lxxy_#/cs_b input during parallel mode configuration possible input after configuration if selectmap port is retained. otherwise, user i/o after configuration chip select for paralle l mode configuration: in parallel (selectmap) modes, this is the active-low chip select signal. this pin becomes a user i/o after configuration unless the selectmap port is retained via the persist bitstream option. io_lxxy_#/rdwr_b input during parallel mode configuration possible input after configuration if selectmap port is retained. otherwise, user i/o after configuration read/write control for parallel mode configuration: in parallel (selectmap) modes, this is the active-low write enable, active-high read enable signal. this pin becomes a user i/o after configuration unless the selectmap port is retained via the persist bitstream option. io_lxxy_#/ busy/dout output during configuration possible output after configuration if selectmap port is retained. otherwise, user i/o after configuration configuration data rate control for parallel mode, serial data output for serial mode: in parallel (selectmap) modes, busy throttles the rate at which configuration data is loaded. this pin becomes a user i/o after configuration unless the selectmap port is retained via the persist bitstream option. in serial modes, dout provides preamble and configuration data to downstream devices in a multi-fpga daisy-chain. this pin becomes a user i/o after configuration.
spartan-3 fpga family: pinout descriptions 4 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r io_lxxy_#/init_b bidirectional (open-drain) during configuration user i/o after configuration initializing configuration memory /detected configuration error: when low, this pin indicates that configuration memory is being cleared. when held low, this pin delays the start of configuration. after this pin is released or configuration memory is cleared, the pin goes high. during configuration, a low on this output indicates that a configuration data error occurred. this pin becomes a user i/o after configuration. dci: digitally controlled impedance reference resistor input pins io_lxxy_#/vrn_# or io/vrn_# input when using dci otherwise, same as i/o dci reference resistor for nmos i/o transistor (per bank): if using dci, a 1% precision impedance-matching resistor is connected between this pin and the vcco supply for this bank. otherwise, this pin is a user i/o. io_lxxy_#/vrp_# or io/vrp_# input when using dci otherwise, same as i/o dci reference resistor for pmos i/o transistor (per bank): if using dci, a 1% precision impedance-matching resistor is connected between this pin and the ground supply. otherwise, this pin is a user i/o. gclk: global clock buffer inputs io_lxxy_#/gclk0, io_lxxy_#/gclk1, io_lxxy_#/gclk2, io_lxxy_#/gclk3, io_lxxy_#/gclk4, io_lxxy_#/gclk5, io_lxxy_#/gclk6, io_lxxy_#/gclk7 input if connected to global clock buffers otherwise, same as i/o global buffer input: direct input to a low-skew global clock buffer. if not connected to a global clock buffer, this pin is a user i/o. vref: i/o bank input reference voltage pins io_lxxy_#/vref_# or io/vref_# voltage supply input when vref pins are used within a bank. otherwise, same as i/o input buffer reference voltage for special i/o standards (per bank): if required to support special i/o standards, all the vref pins within a bank connect to a input threshold voltage source. if not used as input reference voltag e pins, these pins are available as individual user-i/o pins. config: dedicated configuration pins cclk input in slave configuration modes output in master configuration modes configuration clock: the configuration clock signal synchronizes configuration data. prog_b input program/configure device: active low asynchronous reset to configuration logic. asserting prog_b low for an extended period delays the configuration process. this pin has an internal weak pull-up resistor during configuration. ta bl e 2 : spartan-3 pin definitions (continued) pin name direction description
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 5 product specification 1-800-255-7778 r done bidirectional with open-drain or totem-pole output configuration done, delay start-up sequence: a low-to-high output transition on this bidirectional pin signals the end of the configuration process. the fpga produces a low-to-high transition on this pin to indicate that the configuration process is complete. the drivedone bitstream generation option defines whether this pin functions as a totem-pole output that actively drives high or as an open-drain output. an open-drain output requires a pull-up resistor to produce a high logic level. the open-drain option permits the done lines of multiple fpgas to be tied together, so that the common node transitions high only after all of the fpgas have completed configuration. externally holding the open-drain output low delays the start-up sequence, which marks the transition to user mode. m0, m1, m2 input configuration mode selection: these inputs select the configuration mode. the logic levels applied to the mode pins are sampled on the rising edge of init_b. see ta bl e 7 . hswap_en input disable weak pull-up resistors during configuration: a low on this pin enables weak pull-up resistors on all pins that are not actively involved in the configuration process. a high value disables all pull-ups, allowing the non-configuration pins to float. jtag: jtag interface pins tck input jtag test clock: the tck clock signal synchronizes all jtag port operations. tdi input jtag test data input: tdi is the serial data input for all jtag instruction and data registers. tms input jtag test mode select: the serial tms input controls the operation of the jtag port. tdo output jtag test data output: tdo is the serial data output for all jtag instruction and data registers. vcco: i/o bank output voltage supply pins vcco_# supply power supply for output buffer drivers (per bank): these pins power the output drivers within a specific i/o bank. vccaux: auxiliary voltage supply pins vccaux supply power supply for auxiliary circuits: +2.5v power pins for auxiliary circuits, including the digital clock managers (dcms), the dedicated configuration pins (config), and the dedicated jtag pins. all vccaux pins must be connected. vccint: internal core voltage supply pins vccint supply power supply for internal core logic: +1.2v power pins for the internal logic. all pins must be connected. ta bl e 2 : spartan-3 pin definitions (continued) pin name direction description
spartan-3 fpga family: pinout descriptions 6 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r detailed, functional pin descriptions i/o type: unrestricted, general-purpose i/o pins after configuration, i/o-type pins are inputs, outputs, bidi- rectional i/o, three-state outputs, open-drain outputs, or open-source outputs, as defined in the application pins labeled "io" support all selectio? signal standards except differential standards. a given device at most only has a few of these pins. a majority of the general-purpose i/o pins are labeled in the format ?io_lxxy_#?. these pins support all selectio signal standards, including the differential standards such as lvds, ulvds, blvds, rsds, or ldt. for additional information, see the ?iob? section under functional description (module 2 of the spartan-3 data sheet) . differential pair labeling a pin supports differential standards if the pin is labeled in the format ?lxxy_#?. the pin name suffix has the following significance. figure 1 provides a specific example showing a differential input to and a differential output from bank 2. ?l? indicates differential capability. "xx" is a two-digit integer, unique for each bank, that identifies a differential pin-pair. ?y? is replaced by ?p? for the true signal or ?n? for the inverted. these two pins form one differential pin-pair. ?#? is an integer, 0 through 7, indicating the associated i/o bank. if unused, these pins are in a high impedance state. the bit- stream generator option unusedpin enables a weak pull-up or pull-down resistor on all unused i/o pins. behavior from power-on through end of configu- ration during the configuration process, all pins that are not actively involved in the configuration process are in a high-impedance state. the hswap_en input determines whether or not weak pull-up resistors are enabled during configuration. hswap_en = 0 enables the weak pull-up resistors. hswap_en = 1 disables the pull-up resistors allowing the pins to float, which is the desired state for hot-swap applications. gnd: ground supply pins gnd supply ground: ground pins, which are connected to the power supply?s return path. all pins must be connected. n.c.: unconnected package pins n.c. unconnected package pin: these package pins are unconnected. notes: 1. all unused inputs and bidirectional pins must be tied either high or low. for unused enable inputs, apply the level that disa bles the associated function. one common approach is to activate internal pull-up or pull-down resistors. an alternative approach is to externally connect the pin to either vcco or gnd. 2. all outputs are of the totem-pole type ? i.e., they can drive high as well as low logic levels ? except for the cases where ? open drain? is indicated. the latter can only drive a low logic le vel and require a pull-up resistor to produce a high logic level. ta bl e 2 : spartan-3 pin definitions (continued) pin name direction description figure 1: differential pair labelling io_l38p_2 io_l38n_2 io_l39p_2 io_l39n_2 bank 0 bank 1 bank 4 bank 5 bank 2 bank 3 bank 6 bank 7 pair number bank number positive polarity, true driver negative polarity, inverted driver ds099-4_01_042303
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 7 product specification 1-800-255-7778 r dual type: dual-purpos e configuration and i/o pins these pins serve dual purposes . the user-i/o pins are tem- porarily borrowed during the configuration process to load configuration data into the fpga. after configuration, these pins are then usually available as a user i/o in the applica- tion. if a pin is not applicable to the specific configuration mode?controlled by the mode select pins m2, m1, and m0?then the pin behaves as an i/o-type pin. there are 12 dual-purpose configuration pins on every package, six of which are part of i/o bank 4, the other six part of i/o bank 5. only a few of the pins in bank 4 are used in the serial configuration modes. see ?configuration? under functi onal description (module 2 of the spartan-3 data sheet) . see ? pin behavior during configuration , page 15?. serial configuration modes this section describes the dual-purpose pins used during either master or slave serial mode. see ta b l e 7 for mode select pin settings required for serial modes. all such pins are in bank 4 and powered by vcco_4. in both the master and slave serial modes, din is the serial configuration data input. the d1-d7 inputs are unused in serial mode and behave like general-purpose i/o pins. in all the cases, the configuration data is synchronized to the rising edge of the cclk clock signal. the din, dout, and init_b pins can be retained in the application to support reconfiguration by setting the persist bitstream generation option. however, the serial modes do not support device readback. ta bl e 3 : dual-purpose pins used in master or slave serial mode pin name direction description din input serial data input: during the master or slave serial configuration modes, din is the serial configuration data input, and all data is synchronized to the rising cclk edge. after configuration, this pin is available as a user i/o. this signal is located in bank 4 and its output voltage determined by vcco_4. the bitgen option persist permits this pin to retain its configuration function in the user mode. dout output serial data output: in a multi-fpga design where all the fpgas use serial mode, connect the dout output of one fpga?in either master or slave serial mode?to the din input of the next fpga?in slave serial mode?so that configuration data passes from one to the next, in daisy-chain fashion. this ?daisy chain? permits sequential configuration of multiple fpgas. this signal is located in bank 4 and its output voltage determined by vcco_4. the bitgen option persist permits this pin to retain its configuration function in the user mode. init_b bidirectional (open-drain) initializing configuration memory/configuration error: just after power is applied, the fpga prod uces a low-to-high transition on this pin indicating that initialization ( i.e. , clearing) of the configuration memory has finished. before entering the user mode, this pin functions as an open-drain output, which requires a pull-up resistor in order to produce a high logic level. in a multi-fpga design, tie (wire and) the init_b pins from all fpgas together so that the common node transitions high only after all of the fpgas have been successfully initialized. externally holding this pin low beyond th e initialization phase delays the start of configuration. this action stalls the fpga at the configuration step just before the mode select pins are sampled. during configuration, the fpga indicates the occurrence of a data (i.e., crc) error by asserting init_b low. this signal is located in bank 4 and its output voltage determined by vcco_4. the bitgen option persist permits this pin to retain its configuration function in the user mode.
spartan-3 fpga family: pinout descriptions 8 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r parallel configuration modes (selectmap) this section describes the dual-purpose configuration pins used during the master and slave parallel configuration modes, sometimes also calle d the selectmap modes. in both master and slave parallel configuration modes, d0-d7 form the byte-wide configuration data input. see ta bl e 7 for mode select pin settings required for parallel modes. as shown in figure 2 , d0 is the most-significant bit while d7 is the least-significant bit. bits d0-d3 form the high nibble of the byte and bits d4-d7 form the low nibble. in the parallel configuration modes, both the vcco_4 and vcco_5 voltage supplies are required and must both equal the voltage of the attached configuration device, typically either 2.5v or 3.3v. assert low both the chip-select pin, cs_b, and the read/write control pin, rdwr_b, to write the configuration data byte presented on the d0-d7 pins to the fpga on a rising-edge of the configuration clock, cclk. the order of cs_b and rdwr_b does not matter, although rdwr_b must be asserted throughout the configuration process. if rdwr_b is de-asserted during configuration, the fpga aborts the configuration operation. after configuration, these pins are available as general-pur- pose user i/o. however, the selectmap configuration inter- face is optionally available for debugging and dynamic reconfiguration. to use these selectmap pins after configu- ration, set the persist bitstream generation option. the readback debugging option, for example, requires the persist bitstream generation option. during readback mode, assert cs_b low, along with rdwr_b high, to read a configuration data byte from the fpga to the d0-d7 bus on a rising cclk edge. during readback mode, d0-d7 are output pins. in all the cases, the configuration data and control signals are synchronized to the rising edge of the cclk clock sig- nal. i/o bank 4 (vcco_4) i/o bank 5 (vcco_5) high nibble low nibble configuration data byte d0 d1 d2 d3 d4 d5 d6 d7 0xa5 = 1 0 1 0 0 1 0 1 figure 2: configuration data byte mapping to d0-d7 bits
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 9 product specification 1-800-255-7778 r ta bl e 4 : dual-purpose configuration pins for para llel (selectmap) configuration modes pin name direction description d0, d1, d2, d3 input during configuration output during readback configuration data port (high nibble): collectively, the d0-d7 pins are the byte-wide configuration data port for the parallel (selectmap) configuration modes. configuration data is synchronized to the rising edge of cclk clock signal. the d0-d3 pins are the high nibble of the configuration data byte and located in bank 4 and powered by vcco_4. the bitgen option persist permits this pin to retain its configuration function in the user mode. d4, d5, d6, d7 input during configuration output during readback configuration data port (low nibble): the d4-d7 pins are the low nibble of the configuration data byte. however, these signals are located in bank 5 and powered by vcco_5. the bitgen option persist permits this pin to retain its configuration function in the user mode. cs_b input chip select for parallel mode configuration: assert this pin low, together with rdwr_b to write a configuration data byte from the d0-d7 bus to the fpga on a rising cclk edge. during readback, assert this pin low, along with rdwr_b high, to read a configuration data byte from the fpga to the d0-d7 bus on a rising cclk edge. this signal is located in ba nk 5 and powered by vcco_5. the bitgen option persist permits this pin to retain its configuration function in the user mode. cs_b function 0 fpga selected. selectmap inputs are valid on the next rising edge of cclk. 1 fpga deselected. all selectmap inputs are ignored.
spartan-3 fpga family: pinout descriptions 10 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r jtag configuration mode in the jtag configuration mode all dual-purpose configura- tion pins are unused and behave exactly like user-i/o pins, as shown in ta bl e 1 0 . see ta bl e 7 for mode select pin set- tings required for jtag mode. dual-purpose pin i/o standard during configura- tion during configuration, the dual-purpose pins default to cmos input and output levels for the associated vcco voltage supply pins. for example, in the parallel configura- tion modes, both vcco_4 and vcco_5 are required. if connected to +2.5v, then the associated pins conform to the lvcmos25 i/o standard. if connected to +3.3v, then the pins drive lvcmos output levels and accept either lvttl or lvcmos input levels. dual-purpose pin behavior after configuration after the configuration process completes, these pins, if they were borrowed during configuration, become user-i/o pins available to the application. if a dual-purpose configu- ration pin is not used during the configuration process? i.e. , the parallel configuration pins when using serial mode?then the pin behaves exactly like a general-purpose i/o. see i/o type: unrestricted, general-purpose i/o pins section above. rdwr_b input read/write control for parallel mode configuration: in master and slave parallel modes, assert this pin low together with cs_b to write a configuration data byte from the d0-d7 bus to the fpga on a rising cclk edge. once asserted during configuration, rdwr_b must remain asserted until configuration is complete. during readback, assert this pin high with cs_b low to read a configuration data byte from the fpga to the d0-d7 bus on a rising cclk edge. this signal is located in ba nk 5 and powered by vcco_5. the bitgen option persist permits this pin to retain its configuration function in the user mode. busy output configuration data rate control for parallel mode: in the slave and master parallel modes, busy throttles the rate at which configuration data is loaded. busy is only necessary if cclk oper ates at greater than 50 mhz. ignore busy for frequencies of 50 mhz and below. when busy is low, the fpga accepts the next configuration data byte on the next rising cclk edge for which cs_b and rdwr_b are low. when busy is high, the fpga ignores the next configuration data byte. the next configuration data value must be held or reloaded until the next rising cclk edge when busy is lo w. when cs_b is high, busy is in a high impedance state. this signal is located in bank 4 and its output voltage is determined by vcco_4. the bitgen option persist permits this pin to retain its configuration function in the user mode. init_b bidirectional (open-drain) initializing configuration memory/c onfiguration error (active-low): see description under serial configuration modes , page 7 . ta bl e 4 : dual-purpose configuration pins for para llel (selectmap) configuration modes (continued) pin name direction description rdwr_b function 0 if cs_b is low, then load (write) configuration data to the fpga. 1 this option is valid only if the persist bitstream option is set to yes. if cs_b is low, then read configurat ion data from the fpga. busy function 0 the fpga is ready to accept th e next configuration data byte. 1 the fpga is busy processing the current configuration data byte and is not ready to accept the next byte. hi-z if cs_b is high, then busy is high impedance.
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 11 product specification 1-800-255-7778 r dci: user i/o or di gitally controlled impedance resistor reference input these pins are individual user-i/o pins unless one of the i/o standards used in the bank requires the digitally controlled impedance (dci) feature. if dci is used, then 1% precision resistors connected to the vrp_# and vrn_# pins match the impedance on the input or output buffers of the i/o stan- dards that use dci within the bank. the ?#? character in the pin name indicates the associated i/o bank and is an integer, 0 through 7. there are two dci pins per i/o bank, except in the tq144 package, which does not have any dci inputs for bank 5. vrp and vrn impedance resistor reference inputs the 1% precision impedance-matching resistor attached to the vrp_# pin controls the pull-up impedance of pmos transistor in the input or output buffer. consequently, the vrp_# pin must connect to ground. the ?p? character in ?vrp? indicates that this pin controls the i/o buffer?s pmos transistor impedance. the vrp_# pin is used for both single and split termination. the 1% precision impedance-matching resistor attached to the vrn_# pin controls the pull-down impedance of nmos transistor in the input or output buffer. consequently, the vrn_# pin must connect to vcco. the ?n? character in ?vrn? indicates that this pin controls the i/o buffer?s nmos transistor impedance. the vrn_# pin is only used for split termination. each vrn or vrp reference input requires its own resistor. a single resistor cannot be shared between vrn or vrp pins associated with different banks. during configuration, these pins behave exactly like user-i/o pins. the associated dci behavior is not active or valid until after configuration completes. see ?digitally controlled impedance (dci)? under functional description (module 2 of the spartan-3 data sheet) . dci termination types if the i/o in an i/o bank do not use the dci feature, then no external resistors are required and both the vrp_# and vrn_# pins are available for user i/o, as shown in figure 3a . if the i/o standards within the associated i/o bank require single termination?such as gtl_dci, gtlp_dci, or hstl_iii_dci?then only the vrp_# signal connects to a 1% precision impedance-matching resistor, as shown in figure 3b . a resistor is not required for the vrn_# pin. finally, if the i/o standards with the associated i/o bank require split te rmination?such as hstl_i_dci, sstl2_i_dci, sstl2_ii_dci, or lvds_25_dci and lvdsext_25_dci receivers? then both the vrp_# and vrn_# pins connect to separate 1% precision imped- ance-matching resistors, as shown in figure 3c . neither pin is available for user i/o. gclk: global clock buffer inputs or general-purpose i/o pins these pins are user-i/o pins unless they specifically con- nect to one of the eight low-skew global clock buffers on the device, specified using the ibufg primitive. there are eight gclk pins per device and two each appear in the top-edge banks, bank 0 and 1, and the bottom-edge banks, banks 4 and 5. see figure 1 for a picture of bank labeling. during configuration, these pins behave exactly like user-i/o pins. config: dedicated c onfiguration pins the dedicated configuration pins control the configuration process and are not available as user-i/o pins. every pack- age has seven dedicated configuration pins. all con- fig-type pins are powered by the +2.5v vccaux supply. see ?configuration? under functional description (module 2 of the spartan-3 data sheet) . cclk: configuration clock the configuration clock signal on this pin synchronizes the reading or writing of configuration data. this pin is an input for the slave configuration modes, both parallel and serial. after configuration, the cclk pin is in a high-impedance, floating state. by default, cclk optionally is pulled high to vccaux as defined by the cclkpin bitstream selection. any clocks applied to cclk after configuration are ignored unless the bitstream option persist is set to yes, which retains the configuration interface. persist is set to no by default. however, if persist is set to yes, then all clock edges are potentially active events, depending on the other config- uration control signals. the bitstream generator option configrate determines the frequency of the internally -generated cclk oscillator required for the master configuration modes. the actual fre- quency is approximate due to the characteristics of the sili- con oscillator and varies by up to 30% over the temperature and voltage range. by default, cclk operates at approxi- mately 6 mhz. via the configra te option, the oscillator fre- quency is set at approximately 3, 6, 12, 25, or 50 mhz. at power-on, cclk always starts operation at its lowest fre- quency. the device does not start operating at the higher frequency until the configrate control bits are loaded dur- ing the configuration process.
spartan-3 fpga family: pinout descriptions 12 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r prog_b: program/configure device this asynchronous pin initiates the configuration or re-con- figuration processes. a low-going pulse resets the configu- ration logic, initializing th e configuration memory. this initialization process cannot finish until prog_b returns high. asserting prog_b low for an extended period delays the configuration process. at power-up, there is always a weak pull-up resistor to vccaux on this pin. after configuration, the bitstream generator option progpin deter- mines whether or not the weak pull-up resistor is present. by default, the progpin option retains the weak pull-up resistor. after configuration, hold the prog_b input high. any low-going pulse on prog_b restarts the configuration pro- cess. done: configuration done, delay start-up sequence the fpga produces a low-to-high transition on this pin indicating that the configuration process is complete. the bitstream generator option drivedone determines whether this pin functions as a totem-pole output that can drive high or as an open-drain output. if configured as an open-drain output?which is the default behavior?then a pull-up resis- tor is required to produce a high logic level. there is a bit- stream option that provides an internal weak pull-up resistor, otherwise an external pull-up resistor is required. the open-drain option permits the done lines of multiple fpgas to be tied together, so that the common node transi- tions high only after all of the fpgas have completed con- figuration. externally holding the open-drain done pin low delays the start-up sequence, which marks the transition to user mode. once the fpga enters user mode after completing config- uration, the done pin no longer drives the done pin low. the bitstream generator option donepin determines whether or not a weak pull-up resistor is present on the done pin to pull the pin to vccaux. if the weak pull-up resistor is eliminated, then the done pin must be pulled high using an external pull-up resistor or one of the fpgas in the design must actively drive the done pin high via the drivedone bitstream generator option. the bitstream generator option drivedone causes the fpga to actively drive the done output high after configu- ration. this option should only be used in single-fpga designs or on the last fpga in a multi-fpga daisy-chain. by default, the bitstream generator software retains the weak pull-up resistor and does not actively drive the done pin as highlighted in ta bl e 6 . ta b l e 6 shows the interaction of these bitstream options in single- and multi-fpga designs. figure 3: dci termination types ds099-4_03_071304 v cco vrn vrp one of eight i/o banks r ref (1%) r ref (1%) (c) split termination vrn vrp one of eight i/o banks r ref (1%) (b) single termination user i/o user i/o one of eight i/o banks (a) no termination ta bl e 5 : prog_b operation prog_b input response power-up automatically initia tes configuration process. low-going pulse initiate (re-)configuration process and continue to completion. extended low initiate (re-)configuration process and stall process at step where configuration memory is cleared. process is stalled until prog_b returns high. 1 if the configuration process is started, continue to completion. if configuration process is complete, stay in user mode.
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 13 product specification 1-800-255-7778 r m2, m1, m0: configuration mode selection these inputs select the mode to configure the fpga. the logic levels applied to the mode pins are sampled on the ris- ing edge of init_b. in user mode, after configuration successfully completes, any levels applied to these input are ignored. each of the bitstream generator options m0pin, m1pin, and m2pin determines whether a weak pull-up resistor, weak pull-down resistor, or no resistor is present on its respective mode pin, m0, m1, or m2. hswap_en: disable weak pull-up resistors dur- ing configuration a low on this asynchronous pin enables weak pull-up resis- tors on all user i/os, although only until device configuration completes. a high disables the weak pull-up resistors (dur- ing configuration, which is the desired state for some appli- cations. after configuration, hswap_ en essentially becomes a "don?t care" input and any pull-up resistors previously enabled by hswap_en are disabled. if a user i/o in the application requires a weak pull-up resistor after configura- tion, place a pullup primitive on the associated i/o pin. the bitstream generator option hswapenpin determines whether a weak pull-up resistor to vccaux, a weak pull-down resistor, or no resistor is present on hswap_en after configuration. jtag: dedicated jtag port pins these pins are dedicated connections to the four-wire ieee 1532/ieee 1149.1 jtag port, shown in figure 4 and ta bl e 6 : donepin and drivedone bitstream option interaction donepin drivedone single- or multi- fpga design comments pullnone no single external pull-up resistor, with value between 330 ? to 3.3k ? , required on done. pullnone no multi external pull-up resistor, with value between 330 ? to 3.3k ? , required on common node connecting to all done pins. pullnone ye s single ok, no external requirements. pullnone ye s multi drivedone on last device in daisy-chain only. no external requirements. pullup no single ok, but weak pull-up on done pin has slow rise time. may require 330 ? pull-up resistor for high cclk frequencies. pullup no multi external pull-up resistor, with value between 330 ? to 3.3k ? , required on common node connecting to all done pins. pullup ye s single ok, no external requirements. pullup ye s multi drivedone on last device in daisy-chain only. no external requirements. ta bl e 7 : spartan-3 configuration mode select settings configuration mode m2 m1 m0 master serial 0 0 0 slave serial 1 1 1 master parallel 0 1 1 slave parallel 1 1 0 jtag 1 0 1 reserved 0 0 1 reserved 0 1 0 reserved 1 0 0 after configuration x x x notes: 1. x = don?t care, either 0 or 1. ta b l e 8 : hswap_en encoding hswap_en function during configuration 0 enable weak pull-up resistors on all pins not actively involved in the configuration process. pull-ups are only active until configuration co mpletes. see ta b l e 1 0 . 1 no pull-up resistors during configuration. after configuration, user mode x this pin has no function except during device configuration. notes: 1. x = don?t care, either 0 or 1.
spartan-3 fpga family: pinout descriptions 14 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r described in ta b l e 9 . the jtag port is used for bound- ary-scan testing, device configuration, application debug- ging, and possibly an additional serial port for the application. these pins are dedicated and are not available as user-i/o pins. every package has four dedicated jtag pins and these pins are powered by the +2.5v vccaux supply. using jtag port after configuration the jtag port is always active and available before, during, and after fpga configuration. add the bscan_spartan3 primitive to the design to create user-defined jtag instruc- tions and jtag chains to communicate with internal logic. furthermore, the contents of the user id register within the jtag port can be specified as a bitstream generation option. by default, the 32-bit user id register contains 0xffffffff. precautions when using the jtag port in 3.3v environments the jtag port is powered by the +2.5v vccaux power supply. when connecting to a 3.3v interface, the jtag input pins must be current-limited to 10 ma or less using a series resistor. similarly, the tdo pin is a cmos output powered from +2.5v. the tdo output can directly drive a 3.3v input but with reduced noise immunity. see the "3.3v-tolerant configuration interface" section in module 2 for additional details. the following interface precautions are recommended when connecting the jtag port to a 3.3v interface. 1. set any inactive jtag signals, including tck, low when not actively used. 2. limit the drive current into a jtag input to no more than 10 ma. vref: user i/o or in put buffer reference voltage for special interface standards these pins are individual user-i/o pins unless collectively they supply an input reference voltage, vref_#, for any sstl, hstl, gtl, or gtlp i/os implemented in the asso- ciated i/o bank. the ?#? character in the pin name represents an integer, 0 through 7, that indicates the associated i/o bank. the vref function becomes active for this pin whenever a signal standard requiring a reference voltage is used in the associated bank. if used as a user i/o, then each pin behaves as an indepen- dent i/o described in the i/o type section. if used for a ref- erence voltage within a bank, then all vref pins within the bank must be connected to the same reference voltage. spartan-3 devices are designed and characterized to sup- port certain i/o standards when vref is connected to +1.25v, +1.10v, +1.00v, +0.90v, +0.80v, and +0.75v. during configuration, these pins behave exactly like user-i/o pins. figure 4: jtag port data in data out mode select clock tdi tms tck tdo jtag port ds099-4_04_042103 ta bl e 9 : jtag pin descriptions pin name direction description bitstream generation option tck input test clock: the tck clock signal synchronizes all boundary scan operations on its rising edge. the bitgen option tckpin determines whether a weak pull-up resistor, weak pull-down resistor or no resistor is present. tdi input test data input: tdi is the serial data input for all jtag instruction and data registers. this input is sampled on the rising edge of tck. the bitgen option tdipin determines whether a weak pull-up resistor, weak pull-down resistor or no resistor is present. tms input test mode select: the tms input controls the sequence of states through which the jtag tap state machine passes. this input is sampled on the rising edge of tck. the bitgen option tmspin determines whether a weak pull-up resistor, weak pull-down resistor or no resistor is present. tdo output test data output: the tdo pin is the data output for all jtag instruction and data registers. this output is sampled on the rising edge of tck. the tdo output is an active totem-pole driver and is not like the open-collector tdo output on virtex-ii pro? fpgas. the bitgen option tdopin determines whether a weak pull-up resistor, weak pull-down resistor or no resistor is present.
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 15 product specification 1-800-255-7778 r if designing for footprint compatibility across the range of devices in a specific package, and if the vref_# pins within a bank connect to an input reference voltage, then also con- nect any n.c. (not connected) pins on the smaller devices in that package to the input reference voltage. more details are provided later for each package type. n.c. type: unconnected package pins pins marked as ?n.c.? are unconnected for the specific device/package combination. fo r other devices in this same package, this pin may be used as an i/o or vref connec- tion. in both the pinout tables and the footprint diagrams, unconnected pins are noted with either a black diamond symbol ( ? ) or a black square symbol ( ? ). if designing for footprint compatibility across multiple device densities, check the pin types of the other spartan-3 devices available in the same footprint. if the n.c. pin matches to vref pins in other devices, and the vref pins are used in the associated i/o bank, then connect the n.c. to the vref voltage source. vcco type: output volt age supply for i/o bank each i/o bank has its own set of voltage supply pins that determines the output voltage for the output buffers in the i/o bank. furthermore, for some i/o standards such as lvcmos, lvcmos25, lvttl, etc., vcco sets the input threshold voltage on the associated input buffers. spartan-3 devices are designed and characterized to sup- port various i/o standards for vcco values of +1.2v, +1.5v, +1.8v, +2.5v, and +3.3v. most vcco pins are labeled as vcco_# where the ?#? symbol represents the associated i/o bank number, an inte- ger ranging from 0 to 7. in the 144-pin tqfp package (tq144) however, the vcco pins along an edge of the device are combined into a single vcco input. for exam- ple, the vcco inputs for bank 0 and bank 1 along the top edge of the package are combined and relabeled vcco_top. the bottom, left, and right edges are similarly combined. in serial configuration mode, vcco_4 must be at a level compatible with the attached configuration memory or data source. in parallel configuration mode, both vcco_4 and vcco_5 must be at the same compatible voltage level. all vcco inputs to a bank must be connected together and to the voltage supply. furthermore, there must be sufficient supply decoupling to guarantee problem-free operation, as described in xapp623: power distribution system (pds) design: using bypass/ decoupling capacitors . vccint type: voltage supply for internal core logic internal core logic circuits such as the configurable logic blocks (clbs) and programmable interconnect operate from the vccint voltage supply inputs. vccint must be +1.2v. all vccint inputs must be connected together and to the +1.2v voltage supply. furthermore, there must be sufficient supply decoupling to guarantee problem-free operation, as described in xapp623: power distri bution system (pds) design: using bypass/decoupling capacitors . vccaux type: voltage supply for auxiliary logic the vccaux pins supply power to various auxiliary cir- cuits, such as to the digital clock managers (dcms), the jtag pins, and to the dedicated configuration pins (con- fig type). vccaux must be +2.5v. all vccaux inputs must be connected together and to the +2.5v voltage supply. furthermore, there must be sufficient supply decoupling to guarantee problem-free operation, as described in xapp623: power distri bution system (pds) design: using bypass/decoupling capacitors . because vccaux connects to the dcms and the dcms are sensitive to voltage changes, be sure that the vccaux supply and the ground return paths are designed for low noise and low voltage drop, especially that caused by a large number of simultaneous switching i/os. gnd type: ground all gnd pins must be connected and have a low resistance path back to the various vcco, vccint, and vccaux supplies. pin behavior during configuration ta b l e 1 0 shows how various pins behave during the fpga configuration process. the actual behavior depends on the values applied to the m2, m1, and m0 mode select pins and the hswap_en pin. the mode select pins determine which of the dual type pins are active during configuration. in jtag configuration mode, none of the dual-type pins are used for configuration and all behave as user-i/o pins. all dual-type pins not actively used during configuration and all i/o-type, dci-type, vref-type, gclk-type pins are high impedance (floating, three-stated, hi-z) during the configuration process. these pins are indicated in ta bl e 1 0 as shaded table entries or cells. these pins have a weak pull-up resistor to their asso ciated vcco if the hswap_en pin is low. after configuration completes, some pins have optional behavior controlled by the configuration bitstream loaded into the part. for example, via the bitstream, all unused i/o pins can collectively be configured to have a weak pull-up resistor, a weak pull-down resistor, or be left in a high-impedance state.
spartan-3 fpga family: pinout descriptions 16 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r ta bl e 1 0 : pin behavior after power-up, during configuration pin name configuration mode settings bitstream configuration option serial modes selectmap parallel modes jtag mode <1:0:1> master <0:0:0> slave <1:1:1> master <0:1:1> slave <1:1:0> i/o: general-purpose i/o pins io unusedpin io_lxxy_# unusedpin dual: dual-purpose configuration pins io_lxxy_#/ din/d0 din (i) din (i) d0 (i/o) d0 (i/o) persist unusedpin io_lxxy_#/ d1 d1 (i/o) d1 (i/o) persist unusedpin io_lxxy_#/ d2 d2 (i/o) d2 (i/o) persist unusedpin io_lxxy_#/ d3 d3 (i/o) d3 (i/o) persist unusedpin io_lxxy_#/ d4 d4 (i/o) d4 (i/o) persist unusedpin io_lxxy_#/ d5 d5 (i/o) d5 (i/o) persist unusedpin io_lxxy_#/ d6 d6 (i/o) d6 (i/o) persist unusedpin io_lxxy_#/ d7 d7 (i/o) d7 (i/o) persist unusedpin io_lxxy_#/ cs_b cs_b (i) cs_b (i) persist unusedpin io_lxxy_#/ rdwr_b rdwr_b (i) rdwr_b (i) persist unusedpin io_lxxy_#/ busy/dout dout (o) dout (o) busy (o) busy (o) persist unusedpin io_lxxy_#/ init_b init_b (i/od) init_b (i/od) init_b (i/od) init_b (i/od) unusedpin dci: digitally controlled impedance reference resistor input pins io_lxxy_#/ vrn_# unusedpin io/vrn_# unusedpin io_lxxy_#/ vrp_# unusedpin io/vrp_# unusedpin
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 17 product specification 1-800-255-7778 r gclk: global clock buffer inputs io_lxxy_#/ gclk0 through gclk7 unusedpin vref: i/o bank input reference voltage pins io_lxxy_#/ vref_# unusedpin io/vref_# unusedpin config: dedicated configuration pins cclk cclk (o) cclk (i) cclk (o) cclk (i) cclkpin configrate prog_b prog_b (i) (pull-up) prog_b (i) (pull-up) prog_b (i) (pull-up) prog_b (i) (pull-up) prog_b (i), via jprog_b instruction progpin done done (i/od) done (i/od) done (i/od) done (i/od) done (i/od) drivedone donepin donepipe m2 m2=0 (i) m2=1 (i) m2=0 (i) m2=1 (i) m2=1 (i) m2pin m1 m1=0 (i) m1=1 (i) m1=1 (i) m1=1 (i) m1=0 (i) m1pin m0 m0=0 (i) m0=1 (i) m0=1 (i) m0=0 (i) m0=1 (i) m0pin hswap_en hswap_en (i) hswap_en (i) hswap_en (i) hswap_en (i) hswap_en (i) hswapenpin jtag: jtag interface pins tdi tdi (i) tdi (i) tdi (i) tdi (i) tdi (i) tdipin tms tms (i) tms (i) tms (i) tms (i) tms (i) tmspin tck tck (i) tck (i) tck (i) tck (i) tck (i) tckpin tdo tdo (o) tdo (o) tdo (o) tdo (o) tdo (o) tdopin vcco: i/o bank output voltage supply pins vcco_4 (for dual pins) same voltage as external interface same voltage as external interface same voltage as external interface same voltage as external interface vcco_4 vcco_5 (for dual pins) vcco_5 vcco_5 same voltage as external interface same voltage as external interface vcco_5 vcco_# vcco_# vcco_# vcco_# vcco_# vcco_# vccaux: auxiliary voltage supply pins vccaux +2.5v +2.5v +2.5v +2.5v +2.5v ta bl e 1 0 : pin behavior after power-up, during configuration (continued) pin name configuration mode settings bitstream configuration option serial modes selectmap parallel modes jtag mode <1:0:1> master <0:0:0> slave <1:1:1> master <0:1:1> slave <1:1:0>
spartan-3 fpga family: pinout descriptions 18 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r bitstream options ta bl e 1 1 lists the various bitstream options that affect pins on a spartan-3 fpga. the table shows the names of the affected pins, describes the function of the bitstream option, the name of the bitstream generator option variable, and the legal values for each variable. the default option setting for each variable is indicated with bold, underlined text. vccint: internal core voltage supply pins vccint +1.2v +1.2v +1.2v +1.2v +1.2v gnd: ground supply pins gnd gnd gnd gnd gnd gnd notes: 1. #= i/o bank number, an integer from 0 to 7. 2. (i) = input, (o) = output, (od) = open-dra in output, (i/o) = bidirectional, (i/od) = bidirectional with open-drain output. op en-drain output requires pull-up to create logic high level. 3. shaded cell indicates that the pin is high-impedance during c onfiguration. to enable a soft pull-up resistor during configur ation, drive or tie hswap_en low. ta bl e 1 0 : pin behavior after power-up, during configuration (continued) pin name configuration mode settings bitstream configuration option serial modes selectmap parallel modes jtag mode <1:0:1> master <0:0:0> slave <1:1:1> master <0:1:1> slave <1:1:0> ta bl e 1 1 : bitstream options affecting spartan-3 pins affected pin name(s) bitstream generation function option variable name values (default value) all unused i/o pins of type i/o, dual, gclk, dci, vref for all i/o pins that are unused after configuration, this option defines whether the i/os are individually tied to vcco via a weak pull-up resistor, tied ground via a weak pull-down resistor, or left floating. if left floating, the unused pins should be connected to a defined logic level, either from a source internal to the fpga or external. unusedpin pulldown pullup pullnone io_lxxy_#/din, io_lxxy_#/dout, io_lxxy_#/init_b serial configuration mode: if set to yes, then these pins retain their functionality after configuration completes, allowing for device (re-)configuration. readback is not supported in with serial mode. persist no yes io_lxxy_#/d0, io_lxxy_#/d1, io_lxxy_#/d2, io_lxxy_#/d3, io_lxxy_#/d4, io_lxxy_#/d5, io_lxxy_#/d6, io_lxxy_#/d7, io_lxxy_#/cs_b, io_lxxy_#/rdwr_b, io_lxxy_#/busy, io_lxxy_#/init_b parallel configuration mode (also called selectmap): if set to yes, then these pins retain their selectmap functionality after configuration completes, allowing for device readback and for partial or complete (re-)configuration. persist no yes cclk after configuration, this bitstream option either pulls cclk to vccaux via a weak pull-up resistor, or allows cclk to float. cclkpin pullup pullnone cclk for master configuration modes, this option sets the approximate frequency, in mhz, for the internal silicon oscillator. configrate 3, 6 , 12, 25, 50
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 19 product specification 1-800-255-7778 r setting options via bitgen command-line program to set one or more bitstream generator options using the bitgen command-line program, enter bitgen ?g : [: ?] where < variable_name > is one of the entries from ta b l e 1 1 and < value > is one of the possible values for the specified variable. multiple bitstream options may be entered in this manner. for a complete listing of all bitgen options, their possible settings, and their default settings, enter the following com- mand. bitgen -help spartan3 prog_b a weak pull-up resistor to vccaux exists on prog_b during configuration. after configuration, this bitstream option either pulls done to vccaux via a weak pull-up resistor, or allows done to float. progpin pullup pullnone done after configuration, this bitstream option either pulls done to vccaux via a weak pull-up resistor , or allows done to float. see also drivedone option. donepin pullup pullnone done if set to yes, this option allows the fpga?s done pin to drive high when configuration completes. by default, the done is an open-drain output and can only drive low. only single fpgas and the last fpga in a multi-fpga daisy-chain should use this option. drivedone no yes m2 after configuration, this bitstream option either pulls m2 to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows m2 to float. m2pin pullup pulldown pullnone m1 after configuration, this bitstream option either pulls m1 to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows m1 to float. m1pin pullup pulldown pullnone m0 after configuration, this bitstream option either pulls m0 to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows m0 to float. m0pin pullup pulldown pullnone hswap_en after configuration, this bitstream option either pulls hswap_en to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows hswap_en to float. hswapenpin pullup pulldown pullnone tdi after configuration, this bitstream option either pulls tdi to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows tdi to float. tdipin pullup pulldown pullnone tms after configuration, this bitstream option either pulls tms to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows tms to float. tmspin pullup pulldown pullnone tck after configuration, this bitstream option either pulls tck to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows tck to float. tckpin pullup pulldown pullnone tdo after configuration, this bitstream option either pulls tdo to vccaux via a weak pull-up resistor, to ground via a weak pull-down resistor, or allows tdo to float. tdopin pullup pulldown pullnone ta bl e 1 1 : bitstream options affecting spartan-3 pins (continued) affected pin name(s) bitstream generation function option variable name values (default value)
spartan-3 fpga family: pinout descriptions 20 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r setting options in project navigator to set the bitstream generation options in xilinx ise project navigator, right-click on the generate programming file step in the process view and click properties , as shown in figure 5 . click the configuration options tab and modify the avail- able options as required by the application, as shown in figure 6 . figure 5: setting properties for generate programming file step ds099-4_05_030103 figure 6: configuration option settings ds099-4_06_030103
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 21 product specification 1-800-255-7778 r to have the done pin drive high after successful configu- ration, click the startup options tab and check the drive done pin high box, as shown in figure 7 . click ok when finished. again, right-click on the generate programming file step in the process view. this time, choose run or rerun to execute the changes. package overview ta bl e 1 2 shows the nine low-cost, space-saving production package styles for the spartan-3 family. each package style is available as a standard and an environmentally-friendly lead-free (pb-free) option. the pb-free packages include an extra ?g? in the package style name. for example, the stan- dard "vq100" package becomes "vqg100" when ordered as the pb-free option. the mechanical dimensions of the standard and pb-free packages are similar, as shown in the mechanical drawings provided in ta b l e 1 3 . not all spartan-3 densities are available in all packages. however, for a specific package there is a common footprint for that supports the various devices available in that pack- age. see the footprint diagrams that follow. figure 7: setting to drive done pi n high after configuration ds099-4_07_030103 ta bl e 1 2 : spartan-3 family package options package leads type maximum i/o pitch (mm) area (mm) height (mm) vq100 / vqg100 100 very-thin quad flat pack 63 0.5 16 x 16 1.20 tq144 / tqg144 144 thin quad flat pack 97 0.5 22 x 22 1.60 pq208 / pqg208 208 quad flat pack 141 0.5 30.6 x 30.6 4.10 ft256 / ft g 256 256 fine-pitch, thin ball grid array 173 1.0 17 x 17 1.55 fg320 / fgg320 320 fine-pitch ball grid array 221 1.0 19 x 19 2.00 fg456 / fgg456 456 fine-pitch ball grid array 333 1.0 23 x 23 2.60 fg676 / fgg676 676 fine-pitch ball grid array 489 1.0 27 x 27 2.60 fg900 / fgg900 900 fine-pitch ball grid array 633 1.0 31 x 31 2.60 fg1156 / fgg1156 1156 fine-pitch ball grid array 784 1.0 35 x 35 2.60
spartan-3 fpga family: pinout descriptions 22 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r detailed mechanical drawings for each package type are available from the xilinx websit e at the specified location in ta bl e 1 3 . each package has three separate voltage supply inputs?vccint, vccaux, and vcco?and a common ground return, gnd. the numbers of pins dedicated to these functions varies by package, as shown in ta bl e 1 4 . a majority of package pins are user-defined i/o pins. how- ever, the numbers and characteristics of these i/o depends on the device type and the package in which it is available, as shown in ta b l e 1 5 . the table shows the maximum num- ber of single-ended i/o pins available, assuming that all i/o-, dual-, dci-, vref-, and gclk-type pins are used as general-purpose i/o. likewise, the table shows the maxi- mum number of differential pin-pairs available on the pack- age. finally, the table shows how the total maximum user i/os are distributed by pin type, including the number of unconnected?i.e., n.c.?pins on the device. ta bl e 1 3 : xilinx package mechanical drawings package web link (url) vq100 / vqg100 http://www.xilinx.com/bv docs/packages/vq100.pdf tq144 / tqg144 http://www.xilinx.com/bv docs/packages/tq144.pdf pq208 / pqg208 http://www.xilinx.com/bv docs/packages /pq208.pdf ft256 / ftg256 http://www.xilinx.com/bv docs/packages/ft256.pdf fg320 / fgg320 http://www.xilinx.co m/bvdocs/packages/f g320. pdf fg456 / fgg456 http://www.xilinx.com/bv docs/packages/fg456.pdf fg676 / fgg676 http://www.xilinx.com/bv docs/packages/fg676.pdf fg900 /fgg900 http://www.xilinx.com/bv docs/packages/fg900.pdf fg1156 / fgg1156 http://www.xilinx.com/bv docs/packages/fg1156.pdf ta bl e 1 4 : power and ground supply pins by package package vccint vccaux vcco gnd vq100 4 4 8 10 tq144 4 4 12 16 pq208 4 8 12 28 ft256 8 8 24 32 fg320 12 8 28 40 fg456 12 8 40 52 fg676 20 16 64 76 fg900 32 24 80 120 fg1156 40 32 104 184
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 23 product specification 1-800-255-7778 r electronic versions of the package pinout tables and foot- prints are available for down load from the xilinx website. using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. similarly, the ascii-text file is easily parsed by most scripting programs. download the files from the following location: http://www.xilinx.com/bvdoc s/publications/s3_pin.zip ta bl e 1 5 : maximum user i/os by package device package maximum user i/os maximum differential pairs all possible i/o pins by type n.c. i/o dual dci vref gclk xc3s50 vq100 63 29 22 12 14 7 8 0 xc3s200 vq100 63 29 22 12 14 7 8 0 xc3s50 tq144 97 46 51 12 14 12 8 0 xc3s200 tq144 97 46 51 12 14 12 8 0 xc3s400 tq144 97 46 51 12 14 12 8 0 xc3s50 pq208 124 56 72 12 16 16 8 17 xc3s200 pq208 141 62 83 12 16 22 8 0 xc3s400 pq208 141 62 83 12 16 22 8 0 xc3s200 ft256 173 76 113 12 16 24 8 0 xc3s400 ft256 173 76 113 12 16 24 8 0 xc3s1000 ft256 173 76 113 12 16 24 8 0 xc3s400 fg320 221 100 156 12 16 29 8 0 xc3s1000 fg320 221 100 156 12 16 29 8 0 xc3s1500 fg320 221 100 156 12 16 29 8 0 xc3s400 fg456 264 116 196 12 16 32 8 69 xc3s1000 fg456 333 149 261 12 16 36 8 0 xc3s1500 fg456 333 149 261 12 16 36 8 0 xc3s1000 fg676 391 175 315 12 16 40 8 98 xc3s1500 fg676 487 221 403 12 16 48 8 2 xc3s2000 fg676 489 221 405 12 16 48 8 0 xc3s2000 fg900 565 270 481 12 16 48 8 68 xc3s4000 fg900 633 300 549 12 16 48 8 0 xc3s5000 fg900 633 300 549 12 16 48 8 0 xc3s4000 fg1156 712 312 621 12 16 55 8 73 xc3s5000 fg1156 784 344 692 12 16 56 8 1
spartan-3 fpga family: pinout descriptions 24 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r vq100: 100-lead very-thin quad flat package the xc3s50 and the xc3s200 devices are available in the 100-lead very-thin quad flat package, vq100. both devices share a common footprint for this package as shown in ta bl e 1 6 and figure 8 . all the package pins appear in ta bl e 1 6 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. pinout table ta bl e 1 6 : vq100 package pinout bank xc3s50 xc3s200 pin name vq100 pin number type 0 io_l01n_0/vrp_0 p97 dci 0 io_l01p_0/vrn_0 p96 dci 0 io_l31n_0 p92 i/o 0 io_l31p_0/vref_0 p91 vref 0 io_l32n_0/gclk7 p90 gclk 0 io_l32p_0/gclk6 p89 gclk 0 vcco_0 p94 vcco 1io p81 i/o 1 io_l01n_1/vrp_1 p80 dci 1 io_l01p_1/vrn_1 p79 dci 1 io_l31n_1/vref_1 p86 vref 1 io_l31p_1 p85 i/o 1 io_l32n_1/gclk5 p88 gclk 1 io_l32p_1/gclk4 p87 gclk 1 vcco_1 p83 vcco 2 io_l01n_2/vrp_2 p75 dci 2 io_l01p_2/vrn_2 p74 dci 2 io_l21n_2 p72 i/o 2 io_l21p_2 p71 i/o 2 io_l24n_2 p68 i/o 2 io_l24p_2 p67 i/o 2 io_l40n_2 p65 i/o 2 io_l40p_2/vref_2 p64 vref 2 vcco_2 p70 vcco 3io p55 i/o 3io p59 i/o 3 io_l01n_3/vrp_3 p54 dci 3 io_l01p_3/vrn_3 p53 dci 3 io_l24n_3 p61 i/o 3 io_l24p_3 p60 i/o 3 io_l40n_3/vref_3 p63 vref 3 io_l40p_3 p62 i/o 3 vcco_3 p57 vcco 4 io_l01n_4/vrp_4 p50 dci 4 io_l01p_4/vrn_4 p49 dci 4 io_l27n_4/din/d0 p48 dual 4 io_l27p_4/d1 p47 dual 4 io_l30n_4/d2 p44 dual 4 io_l30p_4/d3 p43 dual 4 io_l31n_4/init_b p42 dual 4 io_l31p_4/dout/busy p40 dual 4 io_l32n_4/gclk1 p39 gclk 4 io_l32p_4/gclk0 p38 gclk 4 vcco_4 p46 vcco 5 io_l01n_5/rdwr_b p28 dual 5 io_l01p_5/cs_b p27 dual 5 io_l28n_5/d6 p32 dual 5 io_l28p_5/d7 p30 dual 5 io_l31n_5/d4 p35 dual 5 io_l31p_5/d5 p34 dual 5 io_l32n_5/gclk3 p37 gclk 5 io_l32p_5/gclk2 p36 gclk 5 vcco_5 p31 vcco 6io p17 i/o 6io p21 i/o 6 io_l01n_6/vrp_6 p23 dci 6 io_l01p_6/vrn_6 p22 dci 6 io_l24n_6/vref_6 p16 vref 6 io_l24p_6 p15 i/o 6 io_l40n_6 p14 i/o 6 io_l40p_6/vref_6 p13 vref 6 vcco_6 p19 vcco 7 io_l01n_7/vrp_7 p2 dci 7 io_l01p_7/vrn_7 p1 dci 7 io_l21n_7 p5 i/o 7 io_l21p_7 p4 i/o 7 io_l23n_7 p9 i/o 7 io_l23p_7 p8 i/o 7 io_l40n_7/vref_7 p12 vref 7 io_l40p_7 p11 i/o table 16: vq100 package pinout bank xc3s50 xc3s200 pin name vq100 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 25 product specification 1-800-255-7778 r user i/os by bank ta b l e 1 7 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks on the vq100 pack- age. 7 vcco_7 p6 vcco n/a gnd p3 gnd n/a gnd p10 gnd n/a gnd p20 gnd n/a gnd p29 gnd n/a gnd p41 gnd n/a gnd p56 gnd n/a gnd p66 gnd n/a gnd p73 gnd n/a gnd p82 gnd n/a gnd p95 gnd n/a vccaux p7 vccaux n/a vccaux p33 vccaux n/a vccaux p58 vccaux n/a vccaux p84 vccaux n/a vccint p18 vccint n/a vccint p45 vccint n/a vccint p69 vccint ta bl e 1 6 : vq100 package pinout bank xc3s50 xc3s200 pin name vq100 pin number type n/a vccint p93 vccint vccaux cclk p52 config vccaux done p51 config vccaux hswap_en p98 config vccaux m0 p25 config vccaux m1 p24 config vccaux m2 p26 config vccaux prog_b p99 config vccaux tck p77 jtag vccaux tdi p100 jtag vccaux tdo p76 jtag vccaux tms p78 jtag table 16: vq100 package pinout bank xc3s50 xc3s200 pin name vq100 pin number type ta bl e 1 7 : user i/os per bank in vq100 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 061021 2 172021 2 right 285021 0 385021 0 bottom 4100620 2 580600 2 left 684022 0 785021 0
spartan-3 fpga family: pinout descriptions 26 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r vq100 footprint figure 8: vq100 package footprint (top view). note pin 1 indicator in top-left corner and logo orientation. 22 i/o: unrestricted, general-purpose user i/o 12 dual: configuration pin, then possible user i/o 7 vref: user i/o or input voltage reference for bank 14 dci: user i/o or referenc e resistor input for bank 8 gclk: user i/o or global clock buffer input 8 vcco: output voltage supply for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core voltage supply (+1.2v) 0 n.c.: no unconnected pins in this package 10 gnd: ground 4 vccaux: auxiliary voltage supply (+2.5v) tdi prog_b hswap_en io_l01n_0/vrp_0 io_l01p_0/vrn_0 gn d vcco_0 vccint io_l31n_0 io_l31p_0/vref_0 io_l32n_0/gclk7 io_l32p_0/gclk6 io_l32n_1/gclk5 io_l32p_1/gclk4 io_l31n_1/vref_1 io_l31p_1 vccaux vcco_1 gnd io io_l01n_1/vrp_1 io_l01p_1/vrn_1 tms tck tdo 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 io_l01n_2/vrp_2 2 74 io_l01p_2/vrn_2 3 73 gnd 4 72 io_l21n_2 5 71 io_l21p_2 vcco_7 6 70 vcco_2 vccaux 7 69 vccint 8 68 io_l24n_2 9 67 io_l24p_2 10 66 gnd 11 65 io_l40n_2 12 64 io_l40p_2/vref_2 13 63 io_l40n_3/vref_3 14 62 io_l40p_3 io_l24p_6 io_l40p_7 io_l23p_7 io_l21p_7 io_l21n_7 io_l23n_7 io_l40n_6 15 61 io_l24n_3 16 60 io_l24p_3 io 17 59 io vccint 18 58 vccaux vcco_6 19 57 vcco_3 gnd gnd gnd io_l01n_6/vrp_6 io_l01p_6/vrn_6 io_l24n_6/vref_6 io_l40n_7/vref_7 io_l01p_7/vrn_7 io_l01n_7/vrp_7 io_l40p_6/vref_6 20 56 gnd io 21 55 io 22 54 io_l01n_3/vrp_3 23 53 io_l01p_3/vrn_3 m1 24 52 cclk m0 25 51 done 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 m2 io_l01p_5/cs_b io_l01n_5/rdwr_b gnd io_l28p_5/d7 vcco_5 io_l28n_5/d6 vccaux io_l31p_5/d5 io_l31n_5/d4 io_l32p_5/gclk2 io_l32n_5/gclk3 io_l32p_4/gclk0 io_l32n_4/gclk1 gnd io_l31n_4/init_b io_l30p_4/d3 io_l30n_4/d2 vccint vcco_4 io_l27p_4/d1 io_l27n_4/din/d0 io_l31p_4/dout/busy io_l01p_4/vrn_4 io_l01n_4/vrp_4 bank 6 bank 0 bank 1 bank 3 bank 2 bank 4 (no vref) bank 5 ( no vref, no dci) bank 7 ds099-4_15_042303
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 27 product specification 1-800-255-7778 r tq144: 144-lead thin quad flat package the xc3s50, the xc3s200, and the xc3s400 are avail- able in the 144-lead thin quad flat package, tq144. conse- quently, there is only one footprint for this package as shown in ta b l e 1 8 and figure 9 . the tq144 package only has four separate vcco inputs, unlike the other packages, which have eight separate vcco inputs. the tq144 package has a separate vcco input for the top, bottom, left, and right. however, there are still eight separate i/o banks, as shown in ta b l e 1 8 and figure 9 . banks 0 and 1 share the vcco_top input, banks 2 and 3 share the vcco_right input, banks 4 and 5 share the vcco_bottom input, and banks 6 and 7 share the vcco_left input. all the package pins appear in ta bl e 1 8 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. pinout table ta bl e 1 8 : tq144 package pinout bank xc3s50 xc3s200 xc3s400 pin name tq144 pin number type 0 io_l01n_0/vrp_0 p141 dci 0 io_l01p_0/vrn_0 p140 dci 0 io_l27n_0 p137 i/o 0 io_l27p_0 p135 i/o 0 io_l30n_0 p132 i/o 0 io_l30p_0 p131 i/o 0 io_l31n_0 p130 i/o 0 io_l31p_0/vref_0 p129 vref 0 io_l32n_0/gclk7 p128 gclk 0 io_l32p_0/gclk6 p127 gclk 1 io p116 i/o 1 io_l01n_1/vrp_1 p113 dci 1 io_l01p_1/vrn_1 p112 dci 1 io_l28n_1 p119 i/o 1 io_l28p_1 p118 i/o 1 io_l31n_1/vref_1 p123 vref 1 io_l31p_1 p122 i/o 1 io_l32n_1/gclk5 p125 gclk 1 io_l32p_1/gclk4 p124 gclk 2 io_l01n_2/vrp_2 p108 dci 2 io_l01p_2/vrn_2 p107 dci 2 io_l20n_2 p105 i/o 2 io_l20p_2 p104 i/o 2 io_l21n_2 p103 i/o 2 io_l21p_2 p102 i/o 2 io_l22n_2 p100 i/o 2 io_l22p_2 p99 i/o 2 io_l23n_2/vref_2 p98 vref 2 io_l23p_2 p97 i/o 2 io_l24n_2 p96 i/o 2 io_l24p_2 p95 i/o 2 io_l40n_2 p93 i/o 2 io_l40p_2/vref_2 p92 vref 3 io p76 i/o 3 io_l01n_3/vrp_3 p74 dci 3 io_l01p_3/vrn_3 p73 dci 3 io_l20n_3 p78 i/o 3 io_l20p_3 p77 i/o 3 io_l21n_3 p80 i/o 3 io_l21p_3 p79 i/o 3 io_l22n_3 p83 i/o 3 io_l22p_3 p82 i/o 3 io_l23n_3 p85 i/o 3 io_l23p_3/vref_3 p84 vref 3 io_l24n_3 p87 i/o 3 io_l24p_3 p86 i/o 3 io_l40n_3/vref_3 p90 vref 3 io_l40p_3 p89 i/o 4 io/vref_4 p70 vref 4 io_l01n_4/vrp_4 p69 dci 4 io_l01p_4/vrn_4 p68 dci 4 io_l27n_4/din/d0 p65 dual 4 io_l27p_4/d1 p63 dual 4 io_l30n_4/d2 p60 dual 4 io_l30p_4/d3 p59 dual 4 io_l31n_4/init_b p58 dual 4 io_l31p_4/dout/busy p57 dual 4 io_l32n_4/gclk1 p56 gclk 4 io_l32p_4/gclk0 p55 gclk 5 io/vref_5 p44 vref 5 io_l01n_5/rdwr_b p41 dual 5 io_l01p_5/cs_b p40 dual 5 io_l28n_5/d6 p47 dual table 18: tq144 package pinout (continued) bank xc3s50 xc3s200 xc3s400 pin name tq144 pin number type
spartan-3 fpga family: pinout descriptions 28 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 5 io_l28p_5/d7 p46 dual 5 io_l31n_5/d4 p51 dual 5 io_l31p_5/d5 p50 dual 5 io_l32n_5/gclk3 p53 gclk 5 io_l32p_5/gclk2 p52 gclk 6 io_l01n_6/vrp_6 p36 dci 6 io_l01p_6/vrn_6 p35 dci 6 io_l20n_6 p33 i/o 6 io_l20p_6 p32 i/o 6 io_l21n_6 p31 i/o 6 io_l21p_6 p30 i/o 6 io_l22n_6 p28 i/o 6 io_l22p_6 p27 i/o 6 io_l23n_6 p26 i/o 6 io_l23p_6 p25 i/o 6 io_l24n_6/vref_6 p24 vref 6 io_l24p_6 p23 i/o 6 io_l40n_6 p21 i/o 6 io_l40p_6/vref_6 p20 vref 7 io/vref_7 p4 vref 7 io_l01n_7/vrp_7 p2 dci 7 io_l01p_7/vrn_7 p1 dci 7 io_l20n_7 p6 i/o 7 io_l20p_7 p5 i/o 7 io_l21n_7 p8 i/o 7 io_l21p_7 p7 i/o 7 io_l22n_7 p11 i/o 7 io_l22p_7 p10 i/o 7 io_l23n_7 p13 i/o 7 io_l23p_7 p12 i/o 7 io_l24n_7 p15 i/o 7 io_l24p_7 p14 i/o 7 io_l40n_7/vref_7 p18 vref 7 io_l40p_7 p17 i/o 0,1 vcco_top p126 vcco 0,1 vcco_top p138 vcco 0,1 vcco_top p115 vcco 2,3 vcco_right p106 vcco 2,3 vcco_right p75 vcco 2,3 vcco_right p91 vcco 4,5 vcco_bottom p54 vcco ta bl e 1 8 : tq144 package pinout (continued) bank xc3s50 xc3s200 xc3s400 pin name tq144 pin number type 4,5 vcco_bottom p43 vcco 4,5 vcco_bottom p66 vcco 6,7 vcco_left p19 vcco 6,7 vcco_left p34 vcco 6,7 vcco_left p3 vcco n/a gnd p136 gnd n/a gnd p139 gnd n/a gnd p114 gnd n/a gnd p117 gnd n/a gnd p94 gnd n/a gnd p101 gnd n/a gnd p81 gnd n/a gnd p88 gnd n/a gnd p64 gnd n/a gnd p67 gnd n/a gnd p42 gnd n/a gnd p45 gnd n/a gnd p22 gnd n/a gnd p29 gnd n/a gnd p9 gnd n/a gnd p16 gnd n/a vccaux p134 vccaux n/a vccaux p120 vccaux n/a vccaux p62 vccaux n/a vccaux p48 vccaux n/a vccint p133 vccint n/a vccint p121 vccint n/a vccint p61 vccint n/a vccint p49 vccint vccaux cclk p72 config vccaux done p71 config vccaux hswap_en p142 config vccaux m0 p38 config vccaux m1 p37 config vccaux m2 p39 config vccaux prog_b p143 config vccaux tck p110 jtag vccaux tdi p144 jtag vccaux tdo p109 jtag vccaux tms p111 jtag table 18: tq144 package pinout (continued) bank xc3s50 xc3s200 xc3s400 pin name tq144 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 29 product specification 1-800-255-7778 r user i/os by bank ta bl e 1 9 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks on the tq144 pack- age. ta bl e 1 9 : user i/os per bank in tq144 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 10 5 0 2 1 2 1 9 4 0 2 1 2 right 2 14 10 0 2 2 0 3 15 11 0 2 2 0 bottom 4 11 0 6 2 1 2 5 9 0 6 0 1 2 left 6 14 10 0 2 2 0 7 15 11 0 2 2 0
spartan-3 fpga family: pinout descriptions 30 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r tq144 footprint figure 9: tq144 package footprint (top view). note pin 1 i ndicator in top-left corner and logo orientation. 51 i/o: unrestricted, general-purpose user i/o 12 dual: configuration pin, then possible user i/o 12 vref: user i/o or input voltage reference for bank 14 dci: user i/o or referenc e resistor input for bank 8 gclk: user i/o or global clock buffer input 12 vcco: output voltage supply for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core voltage supply (+1.2v) 0 n.c.: no unconnected pins in this package 16 gnd: ground 4 vccaux: auxiliary voltage supply (+2.5v) io tdi prog_b hswap_en io_l01n_0/vrp_0 io_l01p_0/vrn_0 gnd vcco_top io_l27n_0 gnd io_l27p_0 vccaux vccint io_l30n_0 io_l30p_0 io_l31n_0 io_l31p_0/vref_0 io_l32n_0/gclk 7 io_l32p_0/gclk 6 vcco_top io_l32n_1/gclk 5 io_l32p_1/gclk 4 io_l31n_1/vref_1 io_l31p_1 vccint vccaux io_l28n_1 io_l28p_1 gnd io vcco_top gnd io_l01n_1/vrp_1 io_l01p_1/vrn_1 tms tck tdo 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 io_l01p_7/vrn_7 1 108 io_l01n_2/vrp_2 io_l01n_7/vrp_7 2 107 io_l01p_2/vrn_2 vcco_left 3 x 106 vcco_right io/vref_7 4 105 io_l20n_2 io_l20p_7 5 104 io_l20p_2 io_l20n_7 6 103 io_l21n_2 io_l21p_7 7 102 io_l21p_2 io_l21n_7 8 101 gnd gnd 9 100 io_l22n_2 io_l22p_7 10 99 io_l22p_2 io_l22n_7 11 98 io_l23n_2/vref_2 io_l23p_7 12 97 io_l23p_2 io_l23n_7 13 96 io_l24n_2 io_l24p_7 14 95 io_l24p_2 io_l24n_7 15 94 gnd gnd 16 93 io_l40n_2 io_l40p_7 17 92 io_l40p_2/vref_2 io_l40n_7/vref_7 18 91 vcco_right vcco_left 19 90 io_l40n_3/vref_3 io_l40p_6/vref_6 20 8 9 io_l40p_3 io_l40n_6 21 88 gnd gnd 22 8 7 io_l24n_3 io_l24p_6 23 8 6 io_l24p_3 io_l24n_6/vref_6 24 8 5 io_l23n_3 io_l23p_6 25 8 4 io_l23p_3/vref_3 io_l23n_6 26 8 3 io_l22n_3 io_l22p_6 27 8 2 io_l22p_3 io_l22n_6 28 81 gnd gnd 29 8 0 io_l21n_3 io_l21p_6 30 79 io_l21p_3 io_l21n_6 31 78 io_l20n_3 io_l20p_6 32 77 io_l20p_3 io_l20n_6 33 76 io vcco_left 34 75 vcco_right io_l01p_6/vrn_6 3 5 74 io_l01n_3/vrp_3 io_l01n_6/vrp_6 3 6 73 io_l01p_3/vrn_3 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 m1 m0 m2 io_l01p_5/cs_b _l01n_5/rdwr_b gnd vcco_bottom io/vref_5 gnd io_l28p_5/d7 io_l28n_5/d6 vccaux vccint io_l31p_5/d5 io_l31n_5/d4 io_l32p_5/gclk2 io_l32n_5/gclk3 vcco_bottom io_l32p_4/gclk0 io_l32n_4/gclk1 io_l31p_4/dout/busy io_l31n_4 /init_b io_l30p_4/d3 io_l30n_4/d2 vccint vccaux io_l27p_4/d1 gnd io_l27n_4/din/d0 vcco_bottom gnd io_l01p_4/vrn_4 io_l01n_4/vrp_4 io/vref_4 done cclk bank 5 (no dci) bank 3 bank 2 vcco for top edge vcco for right edge vcco for bottom edge bank 0 bank 1 bank 7 bank 4 bank 6 vcco for left edge ds099-4_08_121103
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 31 product specification 1-800-255-7778 r pq208: 208-lead plast ic quad flat pack the 208-lead plastic quad flat package, pq208, supports three different spartan-3 devices, including the xc3s50, the xc3s200, and the xc3s400. the footprints for the xc3s200 and xc3s400 are identical, as shown in ta bl e 2 0 and figure 10 . the xc3s50, however, has fewer i/o pins resulting in 17 unconnected pins on the pq208 package, labeled as ?n.c.? in ta bl e 2 0 and figure 10 , these uncon- nected pins are indicated with a black diamond symbol ( ? ). all the package pins appear in ta bl e 2 0 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. if there is a difference between the xc3s50 pinout and the pinout for the xc3s200 and xc3s400, then that difference is highlighted in ta b l e 2 0 . if the table entry is shaded grey, then there is an unconnected pin on the xc3s50 that maps to a user-i/o pin on the xc3s200 and xc3s400. if the table entry is shaded tan, then the unconnected pin on the xc3s50 maps to a vref-type pin on the xc3s200 and xc3s400. if the other vref pins in the bank all connect to a voltage reference to support a special i/o standard, then also connect the n.c. pin on the xc3s50 to the same vref voltage. this provides maximum flexibility as you could potentially migrate a design from the xc3s50 device to an xc3s200 or xc3s400 fpga without changing the printed circuit board. pinout table ta bl e 2 0 : pq208 package pinout bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type 0 io io p189 i/o 0 io io p197 i/o 0 n.c. ( ? ) io/vref_0 p200 vref 0 io/vref_0 io/vref_0 p205 vref 0 io_l01n_0/ vrp_0 io_l01n_0/ vrp_0 p204 dci 0 io_l01p_0/ vrn_0 io_l01p_0/ vrn_0 p203 dci 0 io_l25n_0 io_l25n_0 p199 i/o 0 io_l25p_0 io_l25p_0 p198 i/o 0 io_l27n_0 io_l27n_0 p196 i/o 0 io_l27p_0 io_l27p_0 p194 i/o 0 io_l30n_0 io_l30n_0 p191 i/o 0 io_l30p_0 io_l30p_0 p190 i/o 0 io_l31n_0 io_l31n_0 p187 i/o 0 io_l31p_0/ vref_0 io_l31p_0/ vref_0 p185 vref 0 io_l32n_0/ gclk7 io_l32n_0/ gclk7 p184 gclk 0 io_l32p_0/ gclk6 io_l32p_0/ gclk6 p183 gclk 0 vcco_0 vcco_0 p188 vcco 0 vcco_0 vcco_0 p201 vcco 1 io io p167 i/o 1 io io p175 i/o 1 io io p182 i/o 1 io_l01n_1/ vrp_1 io_l01n_1/ vrp_1 p162 dci 1 io_l01p_1/ vrn_1 io_l01p_1/ vrn_1 p161 dci 1 io_l10n_1/ vref_1 io_l10n_1/ vref_1 p166 vref 1 io_l10p_1 io_l10p_1 p165 i/o 1 io_l27n_1 io_l27n_1 p169 i/o 1 io_l27p_1 io_l27p_1 p168 i/o 1 io_l28n_1 io_l28n_1 p172 i/o 1 io_l28p_1 io_l28p_1 p171 i/o 1 io_l31n_1/ vref_1 io_l31n_1/ vref_1 p178 vref 1 io_l31p_1 io_l31p_1 p176 i/o 1 io_l32n_1/ gclk5 io_l32n_1/ gclk5 p181 gclk 1 io_l32p_1/ gclk4 io_l32p_1/ gclk4 p180 gclk 1 vcco_1 vcco_1 p164 vcco 1 vcco_1 vcco_1 p177 vcco 2 n.c. ( ? ) io/vref_2 p154 vref 2 io_l01n_2/ vrp_2 io_l01n_2/ vrp_2 p156 dci 2 io_l01p_2/ vrn_2 io_l01p_2/ vrn_2 p155 dci 2 io_l19n_2 io_l19n_2 p152 i/o 2 io_l19p_2 io_l19p_2 p150 i/o 2 io_l20n_2 io_l20n_2 p149 i/o 2 io_l20p_2 io_l20p_2 p148 i/o 2 io_l21n_2 io_l21n_2 p147 i/o 2 io_l21p_2 io_l21p_2 p146 i/o 2 io_l22n_2 io_l22n_2 p144 i/o 2 io_l22p_2 io_l22p_2 p143 i/o 2 io_l23n_2/ vref_2 io_l23n_2/ vref_2 p141 vref 2 io_l23p_2 io_l23p_2 p140 i/o table 20: pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type
spartan-3 fpga family: pinout descriptions 32 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 2 io_l24n_2 io_l24n_2 p139 i/o 2 io_l24p_2 io_l24p_2 p138 i/o 2 n.c. ( ? ) io_l39n_2 p137 i/o 2 n.c. ( ? ) io_l39p_2 p135 i/o 2 io_l40n_2 io_l40n_2 p133 i/o 2 io_l40p_2/ vref_2 io_l40p_2/ vref_2 p132 vref 2 vcco_2 vcco_2 p136 vcco 2 vcco_2 vcco_2 p153 vcco 3 io_l01n_3/ vrp_3 io_l01n_3/ vrp_3 p107 dci 3 io_l01p_3/ vrn_3 io_l01p_3/ vrn_3 p106 dci 3 n.c. ( ? ) io_l17n_3 p109 i/o 3 n.c. ( ? ) io_l17p_3/ vref_3 p108 vref 3 io_l19n_3 io_l19n_3 p113 i/o 3 io_l19p_3 io_l19p_3 p111 i/o 3 io_l20n_3 io_l20n_3 p115 i/o 3 io_l20p_3 io_l20p_3 p114 i/o 3 io_l21n_3 io_l21n_3 p117 i/o 3 io_l21p_3 io_l21p_3 p116 i/o 3 io_l22n_3 io_l22n_3 p120 i/o 3 io_l22p_3 io_l22p_3 p119 i/o 3 io_l23n_3 io_l23n_3 p123 i/o 3 io_l23p_3/ vref_3 io_l23p_3/ vref_3 p122 vref 3 io_l24n_3 io_l24n_3 p125 i/o 3 io_l24p_3 io_l24p_3 p124 i/o 3 n.c. ( ? ) io_l39n_3 p128 i/o 3 n.c. ( ? ) io_l39p_3 p126 i/o 3 io_l40n_3/ vref_3 io_l40n_3/ vref_3 p131 vref 3 io_l40p_3 io_l40p_3 p130 i/o 3 vcco_3 vcco_3 p110 vcco 3 vcco_3 vcco_3 p127 vcco 4 io io p93 i/o 4 n.c. ( ? ) io p97 i/o 4 io/vref_4 io/vref_4 p85 vref 4 n.c. ( ? ) io/vref_4 p96 vref 4 io/vref_4 io/vref_4 p102 vref 4 io_l01n_4/ vrp_4 io_l01n_4/ vrp_4 p101 dci ta bl e 2 0 : pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type 4 io_l01p_4/ vrn_4 io_l01p_4/ vrn_4 p100 dci 4 io_l25n_4 io_l25n_4 p95 i/o 4 io_l25p_4 io_l25p_4 p94 i/o 4 io_l27n_4/ din/d0 io_l27n_4/ din/d0 p92 dual 4 io_l27p_4/ d1 io_l27p_4/ d1 p90 dual 4 io_l30n_4/ d2 io_l30n_4/ d2 p87 dual 4 io_l30p_4/ d3 io_l30p_4/ d3 p86 dual 4 io_l31n_4/ init_b io_l31n_4/ init_b p83 dual 4 io_l31p_4/ dout/busy io_l31p_4/ dout/busy p81 dual 4 io_l32n_4/ gclk1 io_l32n_4/ gclk1 p80 gclk 4 io_l32p_4/ gclk0 io_l32p_4/ gclk0 p79 gclk 4 vcco_4 vcco_4 p84 vcco 4 vcco_4 vcco_4 p98 vcco 5 io io p63 i/o 5 io io p71 i/o 5 io/vref_5 io/vref_5 p78 vref 5 io_l01n_5/ rdwr_b io_l01n_5/ rdwr_b p58 dual 5 io_l01p_5/ cs_b io_l01p_5/ cs_b p57 dual 5 io_l10n_5/ vrp_5 io_l10n_5/ vrp_5 p62 dci 5 io_l10p_5/ vrn_5 io_l10p_5/ vrn_5 p61 dci 5 io_l27n_5/ vref_5 io_l27n_5/ vref_5 p65 vref 5 io_l27p_5 io_l27p_5 p64 i/o 5 io_l28n_5/ d6 io_l28n_5/ d6 p68 dual 5 io_l28p_5/ d7 io_l28p_5/ d7 p67 dual 5 io_l31n_5/ d4 io_l31n_5/ d4 p74 dual 5 io_l31p_5/ d5 io_l31p_5/ d5 p72 dual 5 io_l32n_5/ gclk3 io_l32n_5/ gclk3 p77 gclk table 20: pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 33 product specification 1-800-255-7778 r 5 io_l32p_5/ gclk2 io_l32p_5/ gclk2 p76 gclk 5 vcco_5 vcco_5 p60 vcco 5 vcco_5 vcco_5 p73 vcco 6 n.c. ( ? ) io/vref_6 p50 vref 6 io_l01n_6/ vrp_6 io_l01n_6/ vrp_6 p52 dci 6 io_l01p_6/ vrn_6 io_l01p_6/ vrn_6 p51 dci 6 io_l19n_6 io_l19n_6 p48 i/o 6 io_l19p_6 io_l19p_6 p46 i/o 6 io_l20n_6 io_l20n_6 p45 i/o 6 io_l20p_6 io_l20p_6 p44 i/o 6 io_l21n_6 io_l21n_6 p43 i/o 6 io_l21p_6 io_l21p_6 p42 i/o 6 io_l22n_6 io_l22n_6 p40 i/o 6 io_l22p_6 io_l22p_6 p39 i/o 6 io_l23n_6 io_l23n_6 p37 i/o 6 io_l23p_6 io_l23p_6 p36 i/o 6 io_l24n_6/ vref_6 io_l24n_6/ vref_6 p35 vref 6 io_l24p_6 io_l24p_6 p34 i/o 6 n.c. ( ? ) io_l39n_6 p33 i/o 6 n.c. ( ? ) io_l39p_6 p31 i/o 6 io_l40n_6 io_l40n_6 p29 i/o 6 io_l40p_6/ vref_6 io_l40p_6/ vref_6 p28 vref 6 vcco_6 vcco_6 p32 vcco 6 vcco_6 vcco_6 p49 vcco 7 io_l01n_7/ vrp_7 io_l01n_7/ vrp_7 p3 dci 7 io_l01p_7/ vrn_7 io_l01p_7/ vrn_7 p2 dci 7 n.c. ( ? ) io_l16n_7 p5 i/o 7 n.c. ( ? ) io_l16p_7/ vref_7 p4 vref 7 io_l19n_7/ vref_7 io_l19n_7/ vref_7 p9 vref 7 io_l19p_7 io_l19p_7 p7 i/o 7 io_l20n_7 io_l20n_7 p11 i/o 7 io_l20p_7 io_l20p_7 p10 i/o 7 io_l21n_7 io_l21n_7 p13 i/o 7 io_l21p_7 io_l21p_7 p12 i/o 7 io_l22n_7 io_l22n_7 p16 i/o ta bl e 2 0 : pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type 7 io_l22p_7 io_l22p_7 p15 i/o 7 io_l23n_7 io_l23n_7 p19 i/o 7 io_l23p_7 io_l23p_7 p18 i/o 7 io_l24n_7 io_l24n_7 p21 i/o 7 io_l24p_7 io_l24p_7 p20 i/o 7 n.c. ( ? ) io_l39n_7 p24 i/o 7 n.c. ( ? ) io_l39p_7 p22 i/o 7 io_l40n_7/ vref_7 io_l40n_7/ vref_7 p27 vref 7 io_l40p_7 io_l40p_7 p26 i/o 7 vcco_7 vcco_7 p6 vcco 7 vcco_7 vcco_7 p23 vcco n/a gnd gnd p1 gnd n/a gnd gnd p186 gnd n/a gnd gnd p195 gnd n/a gnd gnd p202 gnd n/a gnd gnd p163 gnd n/a gnd gnd p170 gnd n/a gnd gnd p179 gnd n/a gnd gnd p134 gnd n/a gnd gnd p145 gnd n/a gnd gnd p151 gnd n/a gnd gnd p157 gnd n/a gnd gnd p112 gnd n/a gnd gnd p118 gnd n/a gnd gnd p129 gnd n/a gnd gnd p82 gnd n/a gnd gnd p91 gnd n/a gnd gnd p99 gnd n/a gnd gnd p105 gnd n/a gnd gnd p53 gnd n/a gnd gnd p59 gnd n/a gnd gnd p66 gnd n/a gnd gnd p75 gnd n/a gnd gnd p30 gnd n/a gnd gnd p41 gnd n/a gnd gnd p47 gnd n/a gnd gnd p8 gnd n/a gnd gnd p14 gnd n/a gnd gnd p25 gnd n/a vccaux vccaux p193 vccaux n/a vccaux vccaux p173 vccaux table 20: pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type
spartan-3 fpga family: pinout descriptions 34 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r user i/os by bank ta b l e 2 1 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks for the xc3s50 in the pq208 package. similarly, ta b l e 2 2 shows how the avail- able user-i/o pins are distributed between the eight i/o banks for the xc3s200 and xc3s400 in the pq208 pack- age. n/a vccaux vccaux p142 vccaux n/a vccaux vccaux p121 vccaux n/a vccaux vccaux p89 vccaux n/a vccaux vccaux p69 vccaux n/a vccaux vccaux p38 vccaux n/a vccaux vccaux p17 vccaux n/a vccint vccint p192 vccint n/a vccint vccint p174 vccint n/a vccint vccint p88 vccint n/a vccint vccint p70 vccint vccaux cclk cclk p104 config vccaux done done p103 config vccaux hswap_en hswap_en p206 config vccaux m0 m0 p55 config ta bl e 2 0 : pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type vccaux m1 m1 p54 config vccaux m2 m2 p56 config vccaux prog_b prog_b p207 config vccaux tck tck p159 jtag vccaux tdi tdi p208 jtag vccaux tdo tdo p158 jtag vccaux tms tms p160 jtag table 20: pq208 package pinout (continued) bank xc3s50 pin name xc3s200 xc3s400 pin name pq208 pin number type ta bl e 2 1 : user i/os per bank for xc3s50 in pq208 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 15 9 0 2 2 2 1 15 9 0 2 2 2 right 2 16 13 0 2 2 0 3 16 12 0 2 2 0 bottom 4 15 3 6 2 2 2 5 15 3 6 2 2 2 left 6 16 12 0 2 2 0 7 16 12 0 2 2 0
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 35 product specification 1-800-255-7778 r ta bl e 2 2 : user i/os per bank for xc3s200 and xc3s400 in pq208 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 16 9 0 2 3 2 1 15 9 0 2 2 2 right 2 19 14 0 2 3 0 3 20 15 0 2 3 0 bottom 4 17 4 6 2 3 2 5 15 3 6 2 2 2 left 6 19 14 0 2 3 0 7 20 15 0 2 3 0
spartan-3 fpga family: pinout descriptions 36 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r pq208 footprint left half of package (top view) xc3s50 (124 max. user i/o) 72 i/o: unrestricted, general-purpose user i/o 16 vref: user i/o or input voltage reference for bank 17 n.c.: unconnected pins for xc3s50 ( ? ) xc3s200, xc3s400 (141 max user i/o) 83 i/o: unrestricted, general-purpose user i/o 22 vref: user i/o or input voltage reference for bank 0 n.c.: no unconnected pins in this package all devices 12 dual: configuration pin, then possible user i/o 8 gclk: user i/o or global clock buffer input 16 dci: user i/o or reference resistor input for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 4 vccint: internal core voltage supply (+1.2v) 12 vcco: output voltage supply for bank 8 vccaux: auxiliary voltage supply (+2.5v) 28 gnd: ground figure 10: pq208 package footprint (top view). note pin 1 indicator in top-left corner and logo orientation. tdi prog_b hswap_en io/vref_0 io_l01n_0/vrp_0 io_l01p_0/vrn_0 gnd vcco_0 io/vref_0 ( ? ) io_l25n_0 io_l25p_0 io io_l27n_0 gnd io_l27p_0 vccaux vccint io_l30n_0 io_l30p_0 io vcco_0 io_l31n_0 gnd io_l31p_0/vref_0 io_l32n_0/gclk7 io_l32p_0/gclk6 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 gnd 1 io_l01p_7/v rn_7 io_l01n_7/vrp_7 ( ? ) io_l16p_7/vref_7 4 ( ? ) io_l16n_7 5 vcco_7 6 io_l19p_7 7 gnd 8 io_l19n_7/vref_7 9 io_l20p_7 10 io_l20n_7 11 io_l21p_7 12 io_l21n_7 13 gnd 14 io_l22p_7 15 io_l22n_7 16 u vcca x 17 io_l23p_7 18 io_l23n_7 19 io_l24p_7 20 io_l24n_7 21 ( ? ) io_l39p_7 22 vcco_7 23 ( ? ) io_l39n_7 24 gnd 25 io_l40p_7 26 io_l40n_7/vref_7 27 io_l40p_6/vref_6 28 io_l40n_6 29 gnd 30 ( ? ) io_l39p_6 31 vcco_6 32 ( ? ) io_l39n_6 33 io_l24p_6 34 io_l24n_6/vref_6 35 io_l23p_6 36 io_l23n_6 37 vccau x 38 io_l22p_6 39 io_l22n_6 40 gnd 41 io_l21p_6 42 io_l21n_6 43 io_l20p_6 44 io_l20n_6 45 io_l19p_6 46 gnd 47 io_l19n_6 48 vcco_6 49 ( ? ) io/vref_6 50 io_l01p_6/v rn_6 51 io_l01n_6/vrp_6 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 gnd m1 m0 m2 io_l01p_5/cs_b io_l01n_5/rdwr_b gnd vcco_5 io_l10p_5/vrn_5 io_l10n_5/vrp_5 io io_l27p_5 io_l27n_5/vref_5 gnd io_l28p_5/d7 io_l28n_5/d6 vccaux vccint io io_l31p_5/d5 vcco_5 io_l31n_5/d4 gnd io_l32p_5/gclk2 io_l32n_5/gclk3 io/vref_5 bank 5 bank 7 bank 6 bank 0 ds099-4_09a_121103 3 2
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 37 product specification 1-800-255-7778 r right half of package (top view) io io_l32n_1/gclk5 io_l32p_1/gclk4 gnd io_l31n_1/vref_1 vcco_1 io_l31p_1 io vccint vccaux io_l28n_1 io_l28p_1 gnd io_l27n_1 io_l27p_1 io io_l10n_1/vref_1 io_l10p_1 vcco_1 gnd io_l01n_1/vrp_1 io_l01p_1/vrn_1 tms tck tdo gnd 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 io_l01n_2/vrp_2 155 io_l01p_2/vrn_2 154 io/vref_2 ( ? ) 153 vcco_2 152 io_l19n_2 151 gnd 150 io_l19p_2 149 io_l20n_2 148 io_l20p_2 147 io_l21n_2 146 io_l21p_2 145 gnd 144 io_l22n_2 143 io_l22p_2 142 vccaux 141 io_l23n_2/vref_2 140 io_l23p_2 139 io_l24n_2 138 io_l24p_2 137 io_l39n_2 ( ? ) 136 vcco_2 135 io_l39p_2 ( ? ) 134 gnd 133 io_l40n_2 132 io_l40p_2/vref_2 131 io_l40n_3/vref_3 130 io_l40p_3 129 gnd 128 io_l39n_3 ( ? ) 127 vcco_3 126 io_l39p_3 ( ? ) 125 io_l24n_3 124 io_l24p_3 123 io_l23n_3 122 io_l23p_3/vref_3 121 vccaux 120 io_l22n_3 119 io_l22p_3 118 gnd 117 io_l21n_3 116 io_l21p_3 115 io_l20n_3 114 io_l20p_3 113 io_l19n_3 112 gnd 111 io_l19p_3 110 vcco_3 109 io_l17n_3 ( ? ) 108 io_l17p_3/vref_3 ( ? ) 107 io_l01n_3/vrp_3 106 io_l01p_3/vrn_3 105 gnd 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 io_l32p_4/gclk0 io_l32n_4/gclk1 io_l31p_4/dout/busy gnd io_l31n_4/init_b vcco_4 io/vref_4 io_l30p_4/d3 io_l30n_4/d2 vccint vccaux io_l27p_4/d1 gnd d io_l27n_4/din/d0 io io_l25p_4 io_l25n_4 ( ? ) io/vref_4 ( ? ) io vcco_4 gnd io_l01p_4/vrn_4 io_l01n_4/vrp_4 io/vref_4 done cclk bank 1 bank 4 bank 3 bank 2 ds099-4_9b_121103
spartan-3 fpga family: pinout descriptions 38 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r ft256: 256-lead fine -pitch thin ball grid array the 256-lead fine-pitch thin ball grid array package, ft256, supports three different spartan-3 devices, including the xc3s200, the xc3s400, and the xc3s1000. the footprints for all three devices are identical, as shown in ta bl e 2 3 and figure 11 . all the package pins appear in ta bl e 2 3 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. pinout table ta bl e 2 3 : ft256 package pinout bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type 0 io a5 i/o 0 io a7 i/o 0 io/vref_0 a3 vref 0 io/vref_0 d5 vref 0 io_l01n_0/vrp_0 b4 dci 0 io_l01p_0/vrn_0 a4 dci 0 io_l25n_0 c5 i/o 0 io_l25p_0 b5 i/o 0 io_l27n_0 e6 i/o 0 io_l27p_0 d6 i/o 0 io_l28n_0 c6 i/o 0 io_l28p_0 b6 i/o 0 io_l29n_0 e7 i/o 0 io_l29p_0 d7 i/o 0 io_l30n_0 c7 i/o 0 io_l30p_0 b7 i/o 0 io_l31n_0 d8 i/o 0 io_l31p_0/vref_0 c8 vref 0 io_l32n_0/gclk7 b8 gclk 0 io_l32p_0/gclk6 a8 gclk 0 vcco_0 e8 vcco 0 vcco_0 f7 vcco 0 vcco_0 f8 vcco 1 io a9 i/o 1 io a12 i/o 1 io c10 i/o 1 io/vref_1 d12 vref 1 io_l01n_1/vrp_1 a14 dci 1 io_l01p_1/vrn_1 b14 dci 1 io_l10n_1/vref_1 a13 vref 1 io_l10p_1 b13 i/o 1 io_l27n_1 b12 i/o 1 io_l27p_1 c12 i/o 1 io_l28n_1 d11 i/o 1 io_l28p_1 e11 i/o 1 io_l29n_1 b11 i/o 1 io_l29p_1 c11 i/o 1 io_l30n_1 d10 i/o 1 io_l30p_1 e10 i/o 1 io_l31n_1/vref_1 a10 vref 1 io_l31p_1 b10 i/o 1 io_l32n_1/gclk5 c9 gclk 1 io_l32p_1/gclk4 d9 gclk 1 vcco_1 e9 vcco 1 vcco_1 f9 vcco 1 vcco_1 f10 vcco 2 io g16 i/o 2 io_l01n_2/vrp_2 b16 dci 2 io_l01p_2/vrn_2 c16 dci 2 io_l16n_2 c15 i/o 2 io_l16p_2 d14 i/o 2 io_l17n_2 d15 i/o 2 io_l17p_2/vref_2 d16 vref 2 io_l19n_2 e13 i/o 2 io_l19p_2 e14 i/o 2 io_l20n_2 e15 i/o 2 io_l20p_2 e16 i/o 2 io_l21n_2 f12 i/o 2 io_l21p_2 f13 i/o 2 io_l22n_2 f14 i/o 2 io_l22p_2 f15 i/o 2 io_l23n_2/vref_2 g12 vref 2 io_l23p_2 g13 i/o 2 io_l24n_2 g14 i/o 2 io_l24p_2 g15 i/o 2 io_l39n_2 h13 i/o 2 io_l39p_2 h14 i/o 2 io_l40n_2 h15 i/o table 23: ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 39 product specification 1-800-255-7778 r 2 io_l40p_2/vref_2 h16 vref 2 vcco_2 g11 vcco 2 vcco_2 h11 vcco 2 vcco_2 h12 vcco 3 io k15 i/o 3 io_l01n_3/vrp_3 p16 dci 3 io_l01p_3/vrn_3 r16 dci 3 io_l16n_3 p15 i/o 3 io_l16p_3 p14 i/o 3 io_l17n_3 n16 i/o 3 io_l17p_3/vref_3 n15 vref 3 io_l19n_3 m14 i/o 3 io_l19p_3 n14 i/o 3 io_l20n_3 m16 i/o 3 io_l20p_3 m15 i/o 3 io_l21n_3 l13 i/o 3 io_l21p_3 m13 i/o 3 io_l22n_3 l15 i/o 3 io_l22p_3 l14 i/o 3 io_l23n_3 k12 i/o 3 io_l23p_3/vref_3 l12 vref 3 io_l24n_3 k14 i/o 3 io_l24p_3 k13 i/o 3 io_l39n_3 j14 i/o 3 io_l39p_3 j13 i/o 3 io_l40n_3/vref_3 j16 vref 3 io_l40p_3 k16 i/o 3 vcco_3 j11 vcco 3 vcco_3 j12 vcco 3 vcco_3 k11 vcco 4 io t12 i/o 4 io t14 i/o 4 io/vref_4 n12 vref 4 io/vref_4 p13 vref 4 io/vref_4 t10 vref 4 io_l01n_4/vrp_4 r13 dci 4 io_l01p_4/vrn_4 t13 dci 4 io_l25n_4 p12 i/o 4 io_l25p_4 r12 i/o 4 io_l27n_4/din/d0 m11 dual ta bl e 2 3 : ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type 4 io_l27p_4/d1 n11 dual 4 io_l28n_4 p11 i/o 4 io_l28p_4 r11 i/o 4 io_l29n_4 m10 i/o 4 io_l29p_4 n10 i/o 4 io_l30n_4/d2 p10 dual 4 io_l30p_4/d3 r10 dual 4 io_l31n_4/init_b n9 dual 4 io_l31p_4/dout/busy p9 dual 4 io_l32n_4/gclk1 r9 gclk 4 io_l32p_4/gclk0 t9 gclk 4 vcco_4 l9 vcco 4 vcco_4 l10 vcco 4 vcco_4 m9 vcco 5 io n5 i/o 5 io p7 i/o 5 io t5 i/o 5 io/vref_5 t8 vref 5 io_l01n_5/rdwr_b t3 dual 5 io_l01p_5/cs_b r3 dual 5 io_l10n_5/vrp_5 t4 dci 5 io_l10p_5/vrn_5 r4 dci 5 io_l27n_5/vref_5 r5 vref 5 io_l27p_5 p5 i/o 5 io_l28n_5/d6 n6 dual 5 io_l28p_5/d7 m6 dual 5 io_l29n_5 r6 i/o 5 io_l29p_5/vref_5 p6 vref 5 io_l30n_5 n7 i/o 5 io_l30p_5 m7 i/o 5 io_l31n_5/d4 t7 dual 5 io_l31p_5/d5 r7 dual 5 io_l32n_5/gclk3 p8 gclk 5 io_l32p_5/gclk2 n8 gclk 5 vcco_5 l7 vcco 5 vcco_5 l8 vcco 5 vcco_5 m8 vcco 6 io k1 i/o 6 io_l01n_6/vrp_6 r1 dci 6 io_l01p_6/vrn_6 p1 dci table 23: ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type
spartan-3 fpga family: pinout descriptions 40 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 6 io_l16n_6 p2 i/o 6 io_l16p_6 n3 i/o 6 io_l17n_6 n2 i/o 6 io_l17p_6/vref_6 n1 vref 6 io_l19n_6 m4 i/o 6 io_l19p_6 m3 i/o 6 io_l20n_6 m2 i/o 6 io_l20p_6 m1 i/o 6 io_l21n_6 l5 i/o 6 io_l21p_6 l4 i/o 6 io_l22n_6 l3 i/o 6 io_l22p_6 l2 i/o 6 io_l23n_6 k5 i/o 6 io_l23p_6 k4 i/o 6 io_l24n_6/vref_6 k3 vref 6 io_l24p_6 k2 i/o 6 io_l39n_6 j4 i/o 6 io_l39p_6 j3 i/o 6 io_l40n_6 j2 i/o 6 io_l40p_6/vref_6 j1 vref 6 vcco_6 j5 vcco 6 vcco_6 j6 vcco 6 vcco_6 k6 vcco 7 io g2 i/o 7 io_l01n_7/vrp_7 c1 dci 7 io_l01p_7/vrn_7 b1 dci 7 io_l16n_7 c2 i/o 7 io_l16p_7/vref_7 c3 vref 7 io_l17n_7 d1 i/o 7 io_l17p_7 d2 i/o 7 io_l19n_7/vref_7 e3 vref 7 io_l19p_7 d3 i/o 7 io_l20n_7 e1 i/o 7 io_l20p_7 e2 i/o 7 io_l21n_7 f4 i/o 7 io_l21p_7 e4 i/o 7 io_l22n_7 f2 i/o 7 io_l22p_7 f3 i/o 7 io_l23n_7 g5 i/o 7 io_l23p_7 f5 i/o ta bl e 2 3 : ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type 7 io_l24n_7 g3 i/o 7 io_l24p_7 g4 i/o 7 io_l39n_7 h3 i/o 7 io_l39p_7 h4 i/o 7 io_l40n_7/vref_7 h1 vref 7 io_l40p_7 g1 i/o 7 vcco_7 g6 vcco 7 vcco_7 h5 vcco 7 vcco_7 h6 vcco n/a gnd a1 gnd n/a gnd a16 gnd n/a gnd b2 gnd n/a gnd b9 gnd n/a gnd b15 gnd n/a gnd f6 gnd n/a gnd f11 gnd n/a gnd g7 gnd n/a gnd g8 gnd n/a gnd g9 gnd n/a gnd g10 gnd n/a gnd h2 gnd n/a gnd h7 gnd n/a gnd h8 gnd n/a gnd h9 gnd n/a gnd h10 gnd n/a gnd j7 gnd n/a gnd j8 gnd n/a gnd j9 gnd n/a gnd j10 gnd n/a gnd j15 gnd n/a gnd k7 gnd n/a gnd k8 gnd n/a gnd k9 gnd n/a gnd k10 gnd n/a gnd l6 gnd n/a gnd l11 gnd n/a gnd r2 gnd n/a gnd r8 gnd n/a gnd r15 gnd n/a gnd t1 gnd table 23: ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 41 product specification 1-800-255-7778 r user i/os by bank ta b l e 2 4 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks on the ft256 package. n/a gnd t16 gnd n/a vccaux a6 vccaux n/a vccaux a11 vccaux n/a vccaux f1 vccaux n/a vccaux f16 vccaux n/a vccaux l1 vccaux n/a vccaux l16 vccaux n/a vccaux t6 vccaux n/a vccaux t11 vccaux n/a vccint d4 vccint n/a vccint d13 vccint n/a vccint e5 vccint n/a vccint e12 vccint n/a vccint m5 vccint n/a vccint m12 vccint n/a vccint n4 vccint ta bl e 2 3 : ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type n/a vccint n13 vccint vccaux cclk t15 config vccaux done r14 config vccaux hswap_en c4 config vccaux m0 p3 config vccaux m1 t2 config vccaux m2 p4 config vccaux prog_b b3 config vccaux tck c14 jtag vccaux tdi a2 jtag vccaux tdo a15 jtag vccaux tms c13 jtag table 23: ft256 package pinout (continued) bank xc3s200 xc3s400 xc3s1000 pin name ft256 pin number type ta bl e 2 4 : user i/os per bank in ft256 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 20 13 0 2 3 2 1 20 13 0 2 3 2 right 2 23 18 0 2 3 0 3 23 18 0 2 3 0 bottom 4 21 8 6 2 3 2 5 20 7 6 2 3 2 left 6 23 18 0 2 3 0 7 23 18 0 2 3 0
spartan-3 fpga family: pinout descriptions 42 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r ft256 footprint figure 11: ft256 package footprint (top view) 113 i/o: unrestricted, general-purpose user i/o 12 dual: configuration pin, then possible user i/o 24 vref: user i/o or input voltage reference for bank 16 dci: user i/o or reference resistor input for bank 8 gclk: user i/o or global clock buffer input 24 vcco: output voltage supply for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 8 vccint: internal core voltage supply (+1.2v) 0 n.c.: no unconnected pins in this package 32 gnd: ground 8 vccaux: auxiliary voltage supply (+2.5v) 10 11 12 13 14 15 16 123456789 a b c d e f g h j k l m n p r t bank 6 bank 3 bank 5 bank 4 bank 7 bank 0 bank 1 bank 2 2 2 3 3 tdi io vref_0 i/o l01p_0 vrn_0 i/o vccaux i/o i/o l32p_0 gclk6 i/o i/o l31n_1 vref_1 vccaux i/o i/o l10n_1 vref_1 i/o l01n_1 vrp_1 tdo i/o l01p_7 vrn_7 prog_b i/o l01n_0 vrp_0 i/o l25p_0 i/o l28p_0 i/o l30p_0 i/o l32n_0 gclk7 i/o l31p_1 i/o l29n_1 i/o l27n_1 i/o l10p_1 i/o l01p_1 vrn_1 i/o l01n_2 vrp_2 i/o l01n_7 vrp_7 i/o l16n_7 i/o l16p_7 vref_7 hswap_ en i/o l25n_0 i/o l28n_0 i/o l30n_0 i/o l31p_0 vref_0 i/o l32n_1 gclk5 i/o i/o l29p_1 i/o l27p_1 tms tck i/o l16n_2 i/o l01p_2 vrn_2 i/o l17n_7 i/o l17p_7 i/o l19p_7 vccint io vref_0 i/o l27p_0 i/o l29p_0 i/o l31n_0 i/o l32p_1 gclk4 i/o l30n_1 i/o l28n_1 io vref_1 vccint i/o l16p_2 i/o l17n_2 i/o l17p_2 vref_2 i/o l20n_7 i/o l20p_7 i/o l19n_7 vref_7 i/o l21p_7 vccint i/o l27n_0 i/o l29n_0 vcco_0 vcco_1 i/o l30p_1 i/o l28p_1 vccint i/o l19n_2 i/o l19p_2 i/o l20n_2 i/o l20p_2 vccaux i/o l22n_7 i/o l22p_7 i/o l21n_7 i/o l23p_7 vcco_0 vcco_0 vcco_1 vcco_1 i/o l21n_2 i/o l21p_2 i/o l22n_2 i/o l22p_2 vccaux i/o l40p_7 i/o i/o l24n_7 i/o l24p_7 i/o l23n_7 vcco_7 vcco_2 i/o l23n_2 vref_2 i/o l23p_2 i/o l24n_2 i/o l24p_2 i/o i/o l40n_7 vref_7 i/o l39n_7 i/o l39p_7 vcco_7 vcco_7 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcco_2 vcco_2 i/o l39n_2 i/o l39p_2 i/o l40n_2 i/o l40p_2 vref_2 i/o l40p_6 vref_6 i/o l40n_6 i/o l39p_6 i/o l39n_6 vcco_6 vcco_6 vcco_3 vcco_3 i/o l39p_3 i/o l39n_3 i/o l40n_3 vref_3 i/o i/o l24p_6 i/o l24n_6 vref_6 i/o l23p_6 i/o l23n_6 vcco_6 vcco_3 i/o l23n_3 i/o l24p_3 i/o l24n_3 i/o i/o l40p_3 vccaux i/o l22p_6 i/o l22n_6 i/o l21p_6 i/o l21n_6 vcco_5 vcco_5 vcco_4 vcco_4 i/o l23p_3 vref_3 i/o l21n_3 i/o l22p_3 i/o l22n_3 vccaux i/o l20p_6 i/o l20n_6 i/o l19p_6 i/o l19n_6 vccint i/o l28p_5 d7 i/o l30p_5 vcco_5 vcco_4 i/o l29n_4 i/o l27n_4 din d0 vccint i/o l21p_3 i/o l19n_3 i/o l20p_3 i/o l20n_3 i/o l17p_6 vref_6 i/o l17n_6 i/o l16p_6 vccint i/o i/o l28n_5 d6 i/o l30n_5 i/o l32p_5 gclk2 i/o l31n_4 init _b i/o l29p_4 i/o l27p_4 d1 io vref_4 vccint i/o l19p_3 i/o l17p_3 vref_3 i/o l17n_3 i/o l01p_6 vrn_6 i/o l16n_6 m0 m2 i/o l27p_5 i/o l29p_5 vref_5 i/o i/o l32n_5 gclk3 i/o l31p_4 dout busy i/o l30n_4 d2 i/o l28n_4 i/o l25n_4 io vref_4 i/o l16p_3 i/o l16n_3 i/o l01n_3 vrp_3 i/o l01n_6 vrp_6 i/o l01p_5 cs_b i/o l10p_5 vrn_5 i/o l27n_5 vref_5 i/o l29n_5 i/o l31p_5 d5 i/o l32n_4 gclk1 i/o l30p_4 d3 i/o l28p_4 i/o l25p_4 i/o l01n_4 vrp_4 done gnd i/o l01p_3 vrn_3 m1 i/o l01n_5 rdwr_b i/o l10n_5 vrp_5 i/o vccaux i/o l31n_5 d4 io vref_5 i/o l32p_4 gclk0 io vref_4 vccaux i/o i/o l01p_4 vrn_4 i/o cclk gnd ds099-4_10_030503
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 43 product specification 1-800-255-7778 r fg320: 320-lead fine -pitch ball grid array the 320-lead fine-pitch ball grid array package, fg320, supports three different spartan-3 devices, including the xc3s400, the xc3s1000, and the xc3s1500. the footprint for all three devices is identical, as shown in ta bl e 2 5 and figure 12 . the fg320 package is an 18 x 18 array of solder balls minus the four center balls. all the package pins appear in ta bl e 2 5 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. pinout table ta bl e 2 5 : fg320 package pinout bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type 0 io d9 i/o 0 io e7 i/o 0 io/vref_0 b3 vref 0 io/vref_0 d6 vref 0 io_l01n_0/vrp_0 a2 dci 0 io_l01p_0/vrn_0 a3 dci 0 io_l09n_0 b4 i/o 0 io_l09p_0 c4 i/o 0 io_l10n_0 c5 i/o 0 io_l10p_0 d5 i/o 0 io_l15n_0 a4 i/o 0 io_l15p_0 a5 i/o 0 io_l25n_0 b5 i/o 0 io_l25p_0 b6 i/o 0 io_l27n_0 c7 i/o 0 io_l27p_0 d7 i/o 0 io_l28n_0 c8 i/o 0 io_l28p_0 d8 i/o 0 io_l29n_0 e8 i/o 0 io_l29p_0 f8 i/o 0 io_l30n_0 a7 i/o 0 io_l30p_0 a8 i/o 0 io_l31n_0 b9 i/o 0 io_l31p_0/vref_0 a9 vref 0 io_l32n_0/gclk7 e9 gclk 0 io_l32p_0/gclk6 f9 gclk 0 vcco_0 b8 vcco 0 vcco_0 c6 vcco 0 vcco_0 g8 vcco 0 vcco_0 g9 vcco 1 io a11 i/o 1 io b13 i/o 1 io d10 i/o 1 io/vref_1 a12 vref 1 io_l01n_1/vrp_1 a16 dci 1 io_l01p_1/vrn_1 a17 dci 1 io_l10n_1/vref_1 a15 vref 1 io_l10p_1 b15 i/o 1 io_l15n_1 c14 i/o 1 io_l15p_1 c15 i/o 1 io_l16n_1 a14 i/o 1 io_l16p_1 b14 i/o 1 io_l24n_1 d14 i/o 1 io_l24p_1 d13 i/o 1 io_l27n_1 e13 i/o 1 io_l27p_1 e12 i/o 1 io_l28n_1 c12 i/o 1 io_l28p_1 d12 i/o 1 io_l29n_1 f11 i/o 1 io_l29p_1 e11 i/o 1 io_l30n_1 c11 i/o 1 io_l30p_1 d11 i/o 1 io_l31n_1/vref_1 a10 vref 1 io_l31p_1 b10 i/o 1 io_l32n_1/gclk5 e10 gclk 1 io_l32p_1/gclk4 f10 gclk 1 vcco_1 b11 vcco 1 vcco_1 c13 vcco 1 vcco_1 g10 vcco 1 vcco_1 g11 vcco 2 io j13 i/o 2 io_l01n_2/vrp_2 c16 dci 2 io_l01p_2/vrn_2 c17 dci 2 io_l16n_2 b18 i/o 2 io_l16p_2 c18 i/o 2 io_l17n_2 d17 i/o 2 io_l17p_2/vref_2 d18 vref 2 io_l19n_2 d16 i/o 2 io_l19p_2 e16 i/o table 25: fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type
spartan-3 fpga family: pinout descriptions 44 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 2 io_l20n_2 e17 i/o 2 io_l20p_2 e18 i/o 2 io_l21n_2 f15 i/o 2 io_l21p_2 e15 i/o 2 io_l22n_2 f14 i/o 2 io_l22p_2 g14 i/o 2 io_l23n_2/vref_2 g18 vref 2 io_l23p_2 f17 i/o 2 io_l24n_2 g15 i/o 2 io_l24p_2 g16 i/o 2 io_l27n_2 h13 i/o 2 io_l27p_2 h14 i/o 2 io_l34n_2/vref_2 h16 vref 2 io_l34p_2 h15 i/o 2 io_l35n_2 h17 i/o 2 io_l35p_2 h18 i/o 2 io_l39n_2 j18 i/o 2 io_l39p_2 j17 i/o 2 io_l40n_2 j15 i/o 2 io_l40p_2/vref_2 j14 vref 2 vcco_2 f16 vcco 2 vcco_2 h12 vcco 2 vcco_2 j12 vcco 3 io k15 i/o 3 io_l01n_3/vrp_3 t17 dci 3 io_l01p_3/vrn_3 t16 dci 3 io_l16n_3 t18 i/o 3 io_l16p_3 u18 i/o 3 io_l17n_3 p16 i/o 3 io_l17p_3/vref_3 r16 vref 3 io_l19n_3 r17 i/o 3 io_l19p_3 r18 i/o 3 io_l20n_3 p18 i/o 3 io_l20p_3 p17 i/o 3 io_l21n_3 p15 i/o 3 io_l21p_3 n15 i/o 3 io_l22n_3 m14 i/o 3 io_l22p_3 n14 i/o 3 io_l23n_3 m15 i/o 3 io_l23p_3/vref_3 m16 vref 3 io_l24n_3 m18 i/o 3 io_l24p_3 n17 i/o ta bl e 2 5 : fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type 3 io_l27n_3 l14 i/o 3 io_l27p_3 l13 i/o 3 io_l34n_3 l15 i/o 3 io_l34p_3/vref_3 l16 vref 3 io_l35n_3 l18 i/o 3 io_l35p_3 l17 i/o 3 io_l39n_3 k13 i/o 3 io_l39p_3 k14 i/o 3 io_l40n_3/vref_3 k17 vref 3 io_l40p_3 k18 i/o 3 vcco_3 k12 vcco 3 vcco_3 l12 vcco 3 vcco_3 n16 vcco 4 io p12 i/o 4 io v14 i/o 4 io/vref_4 r10 vref 4 io/vref_4 u13 vref 4 io/vref_4 v17 vref 4 io_l01n_4/vrp_4 u16 dci 4 io_l01p_4/vrn_4 v16 dci 4 io_l06n_4/vref_4 p14 vref 4 io_l06p_4 r14 i/o 4 io_l09n_4 u15 i/o 4 io_l09p_4 v15 i/o 4 io_l10n_4 t14 i/o 4 io_l10p_4 u14 i/o 4 io_l25n_4 r13 i/o 4 io_l25p_4 p13 i/o 4 io_l27n_4/din/d0 t12 dual 4 io_l27p_4/d1 r12 dual 4 io_l28n_4 v12 i/o 4 io_l28p_4 v11 i/o 4 io_l29n_4 r11 i/o 4 io_l29p_4 t11 i/o 4 io_l30n_4/d2 n11 dual 4 io_l30p_4/d3 p11 dual 4 io_l31n_4/init_b u10 dual 4 io_l31p_4/ dout/busy v10 dual 4 io_l32n_4/gclk1 n10 gclk 4 io_l32p_4/gclk0 p10 gclk 4 vcco_4 m10 vcco table 25: fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 45 product specification 1-800-255-7778 r 4 vcco_4 m11 vcco 4 vcco_4 t13 vcco 4 vcco_4 u11 vcco 5 io n8 i/o 5 io p8 i/o 5 io u6 i/o 5 io/vref_5 r9 vref 5 io_l01n_5/rdwr_b v3 dual 5 io_l01p_5/cs_b v2 dual 5 io_l06n_5 t5 i/o 5 io_l06p_5 t4 i/o 5 io_l10n_5/vrp_5 v4 dci 5 io_l10p_5/vrn_5 u4 dci 5 io_l15n_5 r6 i/o 5 io_l15p_5 r5 i/o 5 io_l16n_5 v5 i/o 5 io_l16p_5 u5 i/o 5 io_l27n_5/vref_5 p6 vref 5 io_l27p_5 p7 i/o 5 io_l28n_5/d6 r7 dual 5 io_l28p_5/d7 t7 dual 5 io_l29n_5 v8 i/o 5 io_l29p_5/vref_5 v7 vref 5 io_l30n_5 r8 i/o 5 io_l30p_5 t8 i/o 5 io_l31n_5/d4 u9 dual 5 io_l31p_5/d5 v9 dual 5 io_l32n_5/gclk3 n9 gclk 5 io_l32p_5/gclk2 p9 gclk 5 vcco_5 m8 vcco 5 vcco_5 m9 vcco 5 vcco_5 t6 vcco 5 vcco_5 u8 vcco 6 io k6 i/o 6 io_l01n_6/vrp_6 t3 dci 6 io_l01p_6/vrn_6 t2 dci 6 io_l16n_6 u1 i/o 6 io_l16p_6 t1 i/o 6 io_l17n_6 r2 i/o 6 io_l17p_6/vref_6 r1 vref 6 io_l19n_6 r3 i/o 6 io_l19p_6 p3 i/o ta bl e 2 5 : fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type 6 io_l20n_6 p2 i/o 6 io_l20p_6 p1 i/o 6 io_l21n_6 n4 i/o 6 io_l21p_6 p4 i/o 6 io_l22n_6 n5 i/o 6 io_l22p_6 m5 i/o 6 io_l23n_6 m3 i/o 6 io_l23p_6 m4 i/o 6 io_l24n_6/vref_6 n2 vref 6 io_l24p_6 m1 i/o 6 io_l27n_6 l6 i/o 6 io_l27p_6 l5 i/o 6 io_l34n_6/vref_6 l3 vref 6 io_l34p_6 l4 i/o 6 io_l35n_6 l2 i/o 6 io_l35p_6 l1 i/o 6 io_l39n_6 k5 i/o 6 io_l39p_6 k4 i/o 6 io_l40n_6 k1 i/o 6 io_l40p_6/vref_6 k2 vref 6 vcco_6 k7 vcco 6 vcco_6 l7 vcco 6 vcco_6 n3 vcco 7 io j6 i/o 7 io_l01n_7/vrp_7 c3 dci 7 io_l01p_7/vrn_7 c2 dci 7 io_l16n_7 c1 i/o 7 io_l16p_7/vref_7 b1 vref 7 io_l17n_7 d1 i/o 7 io_l17p_7 d2 i/o 7 io_l19n_7/vref_7 e3 vref 7 io_l19p_7 d3 i/o 7 io_l20n_7 e2 i/o 7 io_l20p_7 e1 i/o 7 io_l21n_7 e4 i/o 7 io_l21p_7 f4 i/o 7 io_l22n_7 g5 i/o 7 io_l22p_7 f5 i/o 7 io_l23n_7 g1 i/o 7 io_l23p_7 f2 i/o 7 io_l24n_7 g4 i/o 7 io_l24p_7 g3 i/o table 25: fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type
spartan-3 fpga family: pinout descriptions 46 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 7 io_l27n_7 h5 i/o 7 io_l27p_7/vref_7 h6 vref 7 io_l34n_7 h4 i/o 7 io_l34p_7 h3 i/o 7 io_l35n_7 h1 i/o 7 io_l35p_7 h2 i/o 7 io_l39n_7 j1 i/o 7 io_l39p_7 j2 i/o 7 io_l40n_7/vref_7 j5 vref 7 io_l40p_7 j4 i/o 7 vcco_7 f3 vcco 7 vcco_7 h7 vcco 7 vcco_7 j7 vcco n/a gnd a1 gnd n/a gnd a13 gnd n/a gnd a18 gnd n/a gnd a6 gnd n/a gnd b17 gnd n/a gnd b2 gnd n/a gnd c10 gnd n/a gnd c9 gnd n/a gnd f1 gnd n/a gnd f18 gnd n/a gnd g12 gnd n/a gnd g7 gnd n/a gnd h10 gnd n/a gnd h11 gnd n/a gnd h8 gnd n/a gnd h9 gnd n/a gnd j11 gnd n/a gnd j16 gnd n/a gnd j3 gnd n/a gnd j8 gnd n/a gnd k11 gnd n/a gnd k16 gnd n/a gnd k3 gnd n/a gnd k8 gnd n/a gnd l10 gnd n/a gnd l11 gnd n/a gnd l8 gnd n/a gnd l9 gnd n/a gnd m12 gnd ta bl e 2 5 : fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type n/a gnd m7 gnd n/a gnd n1 gnd n/a gnd n18 gnd n/a gnd t10 gnd n/a gnd t9 gnd n/a gnd u17 gnd n/a gnd u2 gnd n/a gnd v1 gnd n/a gnd v13 gnd n/a gnd v18 gnd n/a gnd v6 gnd n/a vccaux b12 vccaux n/a vccaux b7 vccaux n/a vccaux g17 vccaux n/a vccaux g2 vccaux n/a vccaux m17 vccaux n/a vccaux m2 vccaux n/a vccaux u12 vccaux n/a vccaux u7 vccaux n/a vccint f12 vccint n/a vccint f13 vccint n/a vccint f6 vccint n/a vccint f7 vccint n/a vccint g13 vccint n/a vccint g6 vccint n/a vccint m13 vccint n/a vccint m6 vccint n/a vccint n12 vccint n/a vccint n13 vccint n/a vccint n6 vccint n/a vccint n7 vccint vccaux cclk t15 config vccaux done r15 config vccaux hswap_en e6 config vccaux m0 p5 config vccaux m1 u3 config vccaux m2 r4 config vccaux prog_b e5 config vccaux tck e14 jtag vccaux tdi d4 jtag vccaux tdo d15 jtag vccaux tms b16 jtag table 25: fg320 package pinout (continued) bank xc3s400 xc3s1000 xc3s1500 pin name fg320 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 47 product specification 1-800-255-7778 r user i/os by bank table 26 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks on the fg320 pack- age. ta bl e 2 6 : user i/os per bank in fg320 package package edge i/o bank maximum i/o maximum lv d s pairs all possible i/o pins by type i/o dual dci vref gclk to p 0 26 11 19 0 2 3 2 1 26 11 19 0 2 3 2 right 2 29 14 23 0 2 4 0 3 29 14 23 0 2 4 0 bottom 4 27 11 13 6 2 4 2 5 26 11 13 6 2 3 2 left 6 29 14 23 0 2 4 0 7 29 14 23 0 2 4 0
spartan-3 fpga family: pinout descriptions 48 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg320 footprint figure 12: fg320 package footprint (top view) 156 i/o: unrestricted, general-purpose user i/o 12 dual: configuration pin, then possible user i/o 29 vref: user i/o or input voltage reference for bank 16 dci: user i/o or reference resistor input for bank 8 gclk: user i/o or global clock buffer input 28 vcco: output voltage supply for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 12 vccint: internal core voltage supply (+1.2v) 0 n.c.: no unconnected pins in this package 40 gnd: ground 8 vccaux: auxiliary voltage supply (+2.5v) 123456789101112131415161718 a i/o l01n_0 vrp_0 i/o l01p_0 vrn_0 l15n_0 l15p_0 l30n_0 l30p_0 i/o l31p_0 i/o i/o i/o l31n_1 vref_1 vref_1 vref_1 vref_2 vref_2 vref_2 vref_2 vref_3 vref_3 vref_3 vref_3 i/o i/o i/o l16n_1 i/o l10n_1 i/o l01n_1 vrp_1 i/o l01p_1 vrn_1 b i/o l16p_7 vref_7 vref_0 l09n_0 l25n_0 l25p_0 l31n_0 l31p_1 vccaux vccaux i/o i/o l16p_1 i/o l10p_1 tms i/o l16n_2 c l16n_7 i/o l01p_7 vrn_7 i/o i/o l01n_7 vrp_7 l09p_0 l10n_0 l27n_0 l28n_0 i/o l30n_1 i/o l28n_1 vcco_1 i/o l15n_1 i/o l15p_1 i/o l01n_2 vrp_2 i/o l01p_2 vrn_2 i/o l16p_2 d l17n_7 i/o l17p_7 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o l19p_7 tdi l10p_0 vref_0 vref_0 l27p_0 l28p_0 i/o i/o i/o l30p_1 i/o l28p_1 i/o l24p_1 i/o l24n_1 tdo i/o l19n_2 i/o l17n_2 i/o l17p_2 e l20p_7 i/o i/o l20n_7 i/o l19n_7 l21n_7 prog_b hswap_ en l29n_0 i/o l32n_0 i/o l32n_1 gclk5 i/o l29p_1 i/o l27p_1 i/o l27n_1 tck i/o l21p_2 i/o l19p_2 i/o l20n_2 i/o l20p_2 f i/o l23p_7 vcco_7 vcco_7 vcco_0 vcco_0 vcco_0 vcco_0 vcco_7 vcco_6 vcco_6 vcco_6 i/o i/o i/o l21p_7 i/o l22p_7 vccint vccint vccint vccint vccint vccint vccint vccint vccint vccint vccint vccint i/o l29p_0 i/o l32p_0 i/o l32p_1 gclk4 gclk6 gclk7 i/o l29n_1 i/o l22n_2 i/o l21n_2 i/o l23p_2 g i/o l23n_7 vccaux i/o l24p_7 i/o l24n_7 i/o l22n_7 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd vcco_1 vcco_2 vcco_2 vcco_2 vcco_1 vcco_1 i/o l22p_2 i/o l24n_2 i/o l24p_2 i/o l23n_2 h i/o l35n_7 i/o i/o i/o l35p_7 i/o l34p_7 i/o l34n_7 i/o l27n_7 i/o l27p_7 i/o l27n_2 i/o l27p_2 i/o l34p_2 i/o l34n_2 i/o l35n_2 i/o l35p_2 j i/o l39n_7 i/o l39p_7 i/o l40p_7 i/o l40n_7 vref_7 vref_7 vref_7 i/o gnd i/o i/o l40p_2 i/o l40n_2 i/o l39p_2 i/o l39n_2 k i/o l40n_6 i/o l40p_6 i/o l39p_6 i/o l39n_6 i/o gnd i/o l39n_3 i/o l39p_3 i/o i/o l40n_3 i/o l40p_3 l i/o l35p_6 i/o l35n_6 i/o l34n_6 i/o l34p_6 i/o l27p_6 i/o l27n_6 vcco_3 vcco_3 vcco_3 i/o l27p_3 i/o l27n_3 i/o l34n_3 i/o l34p_3 i/o l35p_3 i/o l35n_3 m i/o l24p_6 i/o l23n_6 i/o l23p_6 i/o l22p_6 vcco_5 vcco_5 vcco_5 vcco_5 vcco_4 vcco_4 vcco_4 vcco_4 i/o l22n_3 i/o l23n_3 i/o l23p_3 i/o l24n_3 n i/o l24n_6 i/o l21n_6 i/o l22n_6 i/o i/o l32n_5 i/o l32n_4 i/o l30n_4 d2 i/o l22p_3 i/o l21p_3 i/o l24p_3 p i/o l20p_6 i/o l20n_6 i/o l19p_6 i/o l21p_6 i/o l27n_5 i/o l27p_5 i/o i/o l32p_5 i/o l32p_4 gclk0 gclk1 gclk3 gclk2 i/o l30p_4 d3 i/o i/o l25p_4 i/o l06n_4 i/o l21n_3 i/o l17n_3 i/o l20p_3 i/o l20n_3 r i/o l17p_6 vref_6 vref_6 vref_6 vref_6 i/o l17n_6 m1 m2 m0 i/o l19n_6 i/o l15p_5 i/o l15n_5 i/o l28n_5 d6 i/o l30n_5 i/o i/o i/o l29n_4 i/o l27p_4 d1 i/o l25n_4 i/o l06p_4 done cclk i/o l17p_3 i/o l19n_3 i/o l19p_3 t i/o l16p_6 i/o l01p_6 vrn_6 i/o l01n_6 vrp_6 i/o l06p_5 i/o l06n_5 i/o l28p_5 d7 i/o l30p_5 i/o l29p_4 i/o l27n_4 din d0 i/o l10n_4 i/o l01p_3 vrn_3 i/o l01n_3 vrp_3 i/o l16n_3 u i/o l16n_6 i/o l10p_5 vrn_5 i/o l16p_5 i/o vccaux vccaux vccaux vccaux vccaux i/o l31n_5 d4 i/o l31n_4 init_b i/o i/o l10p_4 i/o l09n_4 i/o l01n_4 vrp_4 i/o l16p_3 v i/o l01p_5 cs_b i/o l01n_5 rdwr_b i/o l10n_5 vrp_5 i/o l16n_5 i/o l29p_5 i/o l29n_5 i/o l31p_5 d5 i/o l31p_4 dout busy i/o l28p_4 i/o l28n_4 i/o i/o l09p_4 i/o l01p_4 vrn_4 i/o vref_4 vref_4 vref_4 vref_4 vref_5 vref_5 vref_5 bank 5 bank 4 bank 0 bank 1 bank 2 bank 3 bank 7 bank 6 ds099-3_16_121103
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 49 product specification 1-800-255-7778 r fg456: 456-lead fine -pitch ball grid array the 456-lead fine-pitch ball grid array package, fg456, supports three different spartan-3 devices, including the xc3s400, the xc3s1000, and the xc3s1500. the foot- prints for the xc3s1000 and xc3s1500 are identical, as shown in ta bl e 2 7 and figure 13 . the xc3s400, however, has fewer i/o pins which consequently results in 69 uncon- nected pins on the fg456 package, labeled as ?n.c.? in ta bl e 2 7 and figure 13 , these unconnected pins are indi- cated with a black diamond symbol ( ? ). all the package pins appear in ta bl e 2 7 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. if there is a difference between the xc3s400 pinout and the pinout for the xc3s1000 and xc3s1500, then that differ- ence is highlighted in ta bl e 2 7 . if the table entry is shaded grey, then there is an unconnected pin on the xc3s400 that maps to a user-i/o pin on the xc3s1000 and xc3s1500. if the table entry is shaded tan, then the unconnected pin on the xc3s400 maps to a vref-type pin on the xc3s1000 and xc3s1500. if the other vref pins in the bank all con- nect to a voltage reference to support a special i/o stan- dard, then also connect the n.c. pin on the xc3s400 to the same vref voltage. this pr ovides maximum flexibility as you could potentially migrate a design from the xc3s400 device to an xc3s1000 or xc3s1500 fpga without chang- ing the printed circuit board. pinout table ta bl e 2 7 : fg456 package pinout bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type 0 io io a10 i/o 0 io io d9 i/o 0 io io d10 i/o 0 io io f6 i/o 0 io/vref_0 io/vref_0 a3 vref 0 io/vref_0 io/vref_0 c7 vref 0 n.c. ( ? ) io/vref_0 e5 vref 0 io/vref_0 io/vref_0 f7 vref 0 io_l01n_0/ vrp_0 io_l01n_0/ vrp_0 b4 dci 0 io_l01p_0/ vrn_0 io_l01p_0/ vrn_0 a4 dci 0 io_l06n_0 io_l06n_0 d5 i/o 0 io_l06p_0 io_l06p_0 c5 i/o 0 io_l09n_0 io_l09n_0 b5 i/o 0 io_l09p_0 io_l09p_0 a5 i/o 0 io_l10n_0 io_l10n_0 e6 i/o 0 io_l10p_0 io_l10p_0 d6 i/o 0 io_l15n_0 io_l15n_0 c6 i/o 0 io_l15p_0 io_l15p_0 b6 i/o 0 io_l16n_0 io_l16n_0 e7 i/o 0 io_l16p_0 io_l16p_0 d7 i/o 0 n.c. ( ? ) io_l19n_0 b7 i/o 0 n.c. ( ? ) io_l19p_0 a7 i/o 0 n.c. ( ? ) io_l22n_0 e8 i/o 0 n.c. ( ? ) io_l22p_0 d8 i/o 0 io_l24n_0 io_l24n_0 b8 i/o 0 io_l24p_0 io_l24p_0 a8 i/o 0 io_l25n_0 io_l25n_0 f9 i/o 0 io_l25p_0 io_l25p_0 e9 i/o 0 io_l27n_0 io_l27n_0 b9 i/o 0 io_l27p_0 io_l27p_0 a9 i/o 0 io_l28n_0 io_l28n_0 f10 i/o 0 io_l28p_0 io_l28p_0 e10 i/o 0 io_l29n_0 io_l29n_0 c10 i/o 0 io_l29p_0 io_l29p_0 b10 i/o 0 io_l30n_0 io_l30n_0 f11 i/o 0 io_l30p_0 io_l30p_0 e11 i/o 0 io_l31n_0 io_l31n_0 d11 i/o 0 io_l31p_0/ vref_0 io_l31p_0/ vref_0 c11 vref 0 io_l32n_0/ gclk7 io_l32n_0/ gclk7 b11 gclk 0 io_l32p_0/ gclk6 io_l32p_0/ gclk6 a11 gclk 0 vcco_0 vcco_0 c8 vcco 0 vcco_0 vcco_0 f8 vcco 0 vcco_0 vcco_0 g9 vcco 0 vcco_0 vcco_0 g10 vcco 0 vcco_0 vcco_0 g11 vcco 1 io io a12 i/o 1 io io e16 i/o 1 io io f12 i/o 1 io io f13 i/o 1 io io f16 i/o 1 io io f17 i/o 1 io/vref_1 io/vref_1 e13 vref 1 n.c. ( ? ) io/vref_1 f14 vref 1 io_l01n_1/ vrp_1 io_l01n_1/ vrp_1 c19 dci 1 io_l01p_1/ vrn_1 io_l01p_1/ vrn_1 b20 dci table 27: fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type
spartan-3 fpga family: pinout descriptions 50 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 1 io_l06n_1/ vref_1 io_l06n_1/ vref_1 a19 vref 1 io_l06p_1 io_l06p_1 b19 i/o 1 io_l09n_1 io_l09n_1 c18 i/o 1 io_l09p_1 io_l09p_1 d18 i/o 1 io_l10n_1/ vref_1 io_l10n_1/ vref_1 a18 vref 1 io_l10p_1 io_l10p_1 b18 i/o 1 io_l15n_1 io_l15n_1 d17 i/o 1 io_l15p_1 io_l15p_1 e17 i/o 1 io_l16n_1 io_l16n_1 b17 i/o 1 io_l16p_1 io_l16p_1 c17 i/o 1 n.c. ( ? ) io_l19n_1 c16 i/o 1 n.c. ( ? ) io_l19p_1 d16 i/o 1 n.c. ( ? ) io_l22n_1 a16 i/o 1 n.c. ( ? ) io_l22p_1 b16 i/o 1 io_l24n_1 io_l24n_1 d15 i/o 1 io_l24p_1 io_l24p_1 e15 i/o 1 io_l25n_1 io_l25n_1 b15 i/o 1 io_l25p_1 io_l25p_1 a15 i/o 1 io_l27n_1 io_l27n_1 d14 i/o 1 io_l27p_1 io_l27p_1 e14 i/o 1 io_l28n_1 io_l28n_1 a14 i/o 1 io_l28p_1 io_l28p_1 b14 i/o 1 io_l29n_1 io_l29n_1 c13 i/o 1 io_l29p_1 io_l29p_1 d13 i/o 1 io_l30n_1 io_l30n_1 a13 i/o 1 io_l30p_1 io_l30p_1 b13 i/o 1 io_l31n_1/ vref_1 io_l31n_1/ vref_1 d12 vref 1 io_l31p_1 io_l31p_1 e12 i/o 1 io_l32n_1/ gclk5 io_l32n_1/ gclk5 b12 gclk 1 io_l32p_1/ gclk4 io_l32p_1/ gclk4 c12 gclk 1 vcco_1 vcco_1 c15 vcco 1 vcco_1 vcco_1 f15 vcco 1 vcco_1 vcco_1 g12 vcco 1 vcco_1 vcco_1 g13 vcco 1 vcco_1 vcco_1 g14 vcco 2 io io c22 i/o 2 io_l01n_2/ vrp_2 io_l01n_2/ vrp_2 c20 dci 2 io_l01p_2/ vrn_2 io_l01p_2/ vrn_2 c21 dci 2 io_l16n_2 io_l16n_2 d20 i/o ta bl e 2 7 : fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type 2 io_l16p_2 io_l16p_2 d19 i/o 2 io_l17n_2 io_l17n_2 d21 i/o 2 io_l17p_2 /vref_2 io_l17p_2/ vref_2 d22 vref 2 io_l19n_2 io_l19n_2 e18 i/o 2 io_l19p_2 io_l19p_2 f18 i/o 2 io_l20n_2 io_l20n_2 e19 i/o 2 io_l20p_2 io_l20p_2 e20 i/o 2 io_l21n_2 io_l21n_2 e21 i/o 2 io_l21p_2 io_l21p_2 e22 i/o 2 io_l22n_2 io_l22n_2 g17 i/o 2 io_l22p_2 io_l22p_2 g18 i/o 2 io_l23n_2 /vref_2 io_l23n_2/ vref_2 f19 vref 2 io_l23p_2 io_l23p_2 g19 i/o 2 io_l24n_2 io_l24n_2 f20 i/o 2 io_l24p_2 io_l24p_2 f21 i/o 2 n.c. ( ? ) io_l26n_2 g20 i/o 2 n.c. ( ? ) io_l26p_2 h19 i/o 2 io_l27n_2 io_l27n_2 g21 i/o 2 io_l27p_2 io_l27p_2 g22 i/o 2 n.c. ( ? ) io_l28n_2 h18 i/o 2 n.c. ( ? ) io_l28p_2 j17 i/o 2 n.c. ( ? ) io_l29n_2 h21 i/o 2 n.c. ( ? ) io_l29p_2 h22 i/o 2 n.c. ( ? ) io_l31n_2 j18 i/o 2 n.c. ( ? ) io_l31p_2 j19 i/o 2 n.c. ( ? ) io_l32n_2 j21 i/o 2 n.c. ( ? ) io_l32p_2 j22 i/o 2 n.c. ( ? ) io_l33n_2 k17 i/o 2 n.c. ( ? ) io_l33p_2 k18 i/o 2 io_l34n_2/ vref_2 io_l34n_2/ vref_2 k19 vref 2 io_l34p_2 io_l34p_2 k20 i/o 2 io_l35n_2 io_l35n_2 k21 i/o 2 io_l35p_2 io_l35p_2 k22 i/o 2 io_l38n_2 io_l38n_2 l17 i/o 2 io_l38p_2 io_l38p_2 l18 i/o 2 io_l39n_2 io_l39n_2 l19 i/o 2 io_l39p_2 io_l39p_2 l20 i/o 2 io_l40n_2 io_l40n_2 l21 i/o 2 io_l40p_2/ vref_2 io_l40p_2/ vref_2 l22 vref 2 vcco_2 vcco_2 h17 vcco 2 vcco_2 vcco_2 h20 vcco table 27: fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 51 product specification 1-800-255-7778 r 2 vcco_2 vcco_2 j16 vcco 2 vcco_2 vcco_2 k16 vcco 2 vcco_2 vcco_2 l16 vcco 3 io io y21 i/o 3 io_l01n_3/ vrp_3 io_l01n_3/ vrp_3 y20 dci 3 io_l01p_3/ vrn_3 io_l01p_3/ vrn_3 y19 dci 3 io_l16n_3 io_l16n_3 w22 i/o 3 io_l16p_3 io_l16p_3 y22 i/o 3 io_l17n_3 io_l17n_3 v19 i/o 3 io_l17p_3/ vref_3 io_l17p_3/ vref_3 w19 vref 3 io_l19n_3 io_l19n_3 w21 i/o 3 io_l19p_3 io_l19p_3 w20 i/o 3 io_l20n_3 io_l20n_3 u19 i/o 3 io_l20p_3 io_l20p_3 v20 i/o 3 io_l21n_3 io_l21n_3 v22 i/o 3 io_l21p_3 io_l21p_3 v21 i/o 3 io_l22n_3 io_l22n_3 t17 i/o 3 io_l22p_3 io_l22p_3 u18 i/o 3 io_l23n_3 io_l23n_3 u21 i/o 3 io_l23p_3/ vref_3 io_l23p_3/ vref_3 u20 vref 3 io_l24n_3 io_l24n_3 r18 i/o 3 io_l24p_3 io_l24p_3 t18 i/o 3 n.c. ( ? ) io_l26n_3 t20 i/o 3 n.c. ( ? ) io_l26p_3 t19 i/o 3 io_l27n_3 io_l27n_3 t22 i/o 3 io_l27p_3 io_l27p_3 t21 i/o 3 n.c. ( ? ) io_l28n_3 r22 i/o 3 n.c. ( ? ) io_l28p_3 r21 i/o 3 n.c. ( ? ) io_l29n_3 p19 i/o 3 n.c. ( ? ) io_l29p_3 r19 i/o 3 n.c. ( ? ) io_l31n_3 p18 i/o 3 n.c. ( ? ) io_l31p_3 p17 i/o 3 n.c. ( ? ) io_l32n_3 p22 i/o 3 n.c. ( ? ) io_l32p_3 p21 i/o 3 n.c. ( ? ) io_l33n_3 n18 i/o 3 n.c. ( ? ) io_l33p_3 n17 i/o 3 io_l34n_3 io_l34n_3 n20 i/o 3 io_l34p_3/ vref_3 io_l34p_3/ vref_3 n19 vref 3 io_l35n_3 io_l35n_3 n22 i/o 3 io_l35p_3 io_l35p_3 n21 i/o 3 io_l38n_3 io_l38n_3 m18 i/o ta bl e 2 7 : fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type 3 io_l38p_3 io_l38p_3 m17 i/o 3 io_l39n_3 io_l39n_3 m20 i/o 3 io_l39p_3 io_l39p_3 m19 i/o 3 io_l40n_3/ vref_3 io_l40n_3/ vref_3 m22 vref 3 io_l40p_3 io_l40p_3 m21 i/o 3 vcco_3 vcco_3 m16 vcco 3 vcco_3 vcco_3 n16 vcco 3 vcco_3 vcco_3 p16 vcco 3 vcco_3 vcco_3 r17 vcco 3 vcco_3 vcco_3 r20 vcco 4 io io u16 i/o 4 io io u17 i/o 4 io io w13 i/o 4 io io w14 i/o 4 io/vref_4 io/vref_4 ab13 vref 4 io/vref_4 io/vref_4 v18 vref 4 io/vref_4 io/vref_4 y16 vref 4 io_l01n_4/ vrp_4 io_l01n_4/ vrp_4 aa20 dci 4 io_l01p_4/ vrn_4 io_l01p_4/ vrn_4 ab20 dci 4 n.c. ( ? ) io_l05n_4 aa19 i/o 4 n.c. ( ? ) io_l05p_4 ab19 i/o 4 io_l06n_4/ vref_4 io_l06n_4/ vref_4 w18 vref 4 io_l06p_4 io_l06p_4 y18 i/o 4 io_l09n_4 io_l09n_4 aa18 i/o 4 io_l09p_4 io_l09p_4 ab18 i/o 4 io_l10n_4 io_l10n_4 v17 i/o 4 io_l10p_4 io_l10p_4 w17 i/o 4 io_l15n_4 io_l15n_4 y17 i/o 4 io_l15p_4 io_l15p_4 aa17 i/o 4 io_l16n_4 io_l16n_4 v16 i/o 4 io_l16p_4 io_l16p_4 w16 i/o 4 n.c. ( ? ) io_l19n_4 aa16 i/o 4 n.c. ( ? ) io_l19p_4 ab16 i/o 4 n.c. ( ? ) io_l22n_4/ vref_4 v15 vref 4 n.c. ( ? ) io_l22p_4 w15 i/o 4 io_l24n_4 io_l24n_4 aa15 i/o 4 io_l24p_4 io_l24p_4 ab15 i/o 4 io_l25n_4 io_l25n_4 u14 i/o 4 io_l25p_4 io_l25p_4 v14 i/o 4 io_l27n_4/ din/d0 io_l27n_4/ din/d0 aa14 dual table 27: fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type
spartan-3 fpga family: pinout descriptions 52 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 4 io_l27p_4/ d1 io_l27p_4/ d1 ab14 dual 4 io_l28n_4 io_l28n_4 u13 i/o 4 io_l28p_4 io_l28p_4 v13 i/o 4 io_l29n_4 io_l29n_4 y13 i/o 4 io_l29p_4 io_l29p_4 aa13 i/o 4 io_l30n_4/ d2 io_l30n_4/ d2 u12 dual 4 io_l30p_4/ d3 io_l30p_4/ d3 v12 dual 4 io_l31n_4/ init_b io_l31n_4/ init_b w12 dual 4 io_l31p_4/ dout/busy io_l31p_4/ dout/busy y12 dual 4 io_l32n_4/ gclk1 io_l32n_4/ gclk1 aa12 gclk 4 io_l32p_4/ gclk0 io_l32p_4/ gclk0 ab12 gclk 4 vcco_4 vcco_4 t12 vcco 4 vcco_4 vcco_4 t13 vcco 4 vcco_4 vcco_4 t14 vcco 4 vcco_4 vcco_4 u15 vcco 4 vcco_4 vcco_4 y15 vcco 5 io io u7 i/o 5 n.c. ( ? ) io u9 i/o 5 io io u10 i/o 5 io io u11 i/o 5 io io v7 i/o 5 io io v10 i/o 5 io/vref_5 io/vref_5 ab11 vref 5 io/vref_5 io/vref_5 u6 vref 5 io_l01n_5/ rdwr_b io_l01n_5/ rdwr_b y4 dual 5 io_l01p_5/ cs_b io_l01p_5/ cs_b aa3 dual 5 io_l06n_5 io_l06n_5 ab4 i/o 5 io_l06p_5 io_l06p_5 aa4 i/o 5 io_l09n_5 io_l09n_5 y5 i/o 5 io_l09p_5 io_l09p_5 w5 i/o 5 io_l10n_5/ vrp_5 io_l10n_5/ vrp_5 ab5 dci 5 io_l10p_5/ vrn_5 io_l10p_5/ vrn_5 aa5 dci 5 io_l15n_5 io_l15n_5 w6 i/o 5 io_l15p_5 io_l15p_5 v6 i/o 5 io_l16n_5 io_l16n_5 aa6 i/o 5 io_l16p_5 io_l16p_5 y6 i/o ta bl e 2 7 : fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type 5 n.c. ( ? ) io_l19n_5 y7 i/o 5 n.c. ( ? ) io_l19p_5/ vref_5 w7 vref 5 n.c. ( ? ) io_l22n_5 ab7 i/o 5 n.c. ( ? ) io_l22p_5 aa7 i/o 5 io_l24n_5 io_l24n_5 w8 i/o 5 io_l24p_5 io_l24p_5 v8 i/o 5 io_l25n_5 io_l25n_5 ab8 i/o 5 io_l25p_5 io_l25p_5 aa8 i/o 5 io_l27n_5/ vref_5 io_l27n_5/ vref_5 w9 vref 5 io_l27p_5 io_l27p_5 v9 i/o 5 io_l28n_5/ d6 io_l28n_5/ d6 ab9 dual 5 io_l28p_5/ d7 io_l28p_5/ d7 aa9 dual 5 io_l29n_5 io_l29n_5 y10 i/o 5 io_l29p_5/ vref_5 io_l29p_5/ vref_5 w10 vref 5 io_l30n_5 io_l30n_5 ab10 i/o 5 io_l30p_5 io_l30p_5 aa10 i/o 5 io_l31n_5/ d4 io_l31n_5/ d4 w11 dual 5 io_l31p_5/ d5 io_l31p_5/ d5 v11 dual 5 io_l32n_5/ gclk3 io_l32n_5/ gclk3 aa11 gclk 5 io_l32p_5/ gclk2 io_l32p_5/ gclk2 y11 gclk 5 vcco_5 vcco_5 t9 vcco 5 vcco_5 vcco_5 t10 vcco 5 vcco_5 vcco_5 t11 vcco 5 vcco_5 vcco_5 u8 vcco 5 vcco_5 vcco_5 y8 vcco 6 io io y1 i/o 6 io_l01n_6/ vrp_6 io_l01n_6/ vrp_6 y3 dci 6 io_l01p_6/ vrn_6 io_l01p_6/ vrn_6 y2 dci 6 io_l16n_6 io_l16n_6 w4 i/o 6 io_l16p_6 io_l16p_6 w3 i/o 6 io_l17n_6 io_l17n_6 w2 i/o 6 io_l17p_6/ vref_6 io_l17p_6/ vref_6 w1 vref 6 io_l19n_6 io_l19n_6 v5 i/o 6 io_l19p_6 io_l19p_6 u5 i/o 6 io_l20n_6 io_l20n_6 v4 i/o table 27: fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 53 product specification 1-800-255-7778 r 6 io_l20p_6 io_l20p_6 v3 i/o 6 io_l21n_6 io_l21n_6 v2 i/o 6 io_l21p_6 io_l21p_6 v1 i/o 6 io_l22n_6 io_l22n_6 t6 i/o 6 io_l22p_6 io_l22p_6 t5 i/o 6 io_l23n_6 io_l23n_6 u4 i/o 6 io_l23p_6 io_l23p_6 t4 i/o 6 io_l24n_6/ vref_6 io_l24n_6/ vref_6 u3 vref 6 io_l24p_6 io_l24p_6 u2 i/o 6 n.c. ( ? ) io_l26n_6 t3 i/o 6 n.c. ( ? ) io_l26p_6 r4 i/o 6 io_l27n_6 io_l27n_6 t2 i/o 6 io_l27p_6 io_l27p_6 t1 i/o 6 n.c. ( ? ) io_l28n_6 r5 i/o 6 n.c. ( ? ) io_l28p_6 p6 i/o 6 n.c. ( ? ) io_l29n_6 r2 i/o 6 n.c. ( ? ) io_l29p_6 r1 i/o 6 n.c. ( ? ) io_l31n_6 p5 i/o 6 n.c. ( ? ) io_l31p_6 p4 i/o 6 n.c. ( ? ) io_l32n_6 p2 i/o 6 n.c. ( ? ) io_l32p_6 p1 i/o 6 n.c. ( ? ) io_l33n_6 n6 i/o 6 n.c. ( ? ) io_l33p_6 n5 i/o 6 io_l34n_6/ vref_6 io_l34n_6/ vref_6 n4 vref 6 io_l34p_6 io_l34p_6 n3 i/o 6 io_l35n_6 io_l35n_6 n2 i/o 6 io_l35p_6 io_l35p_6 n1 i/o 6 io_l38n_6 io_l38n_6 m6 i/o 6 io_l38p_6 io_l38p_6 m5 i/o 6 io_l39n_6 io_l39n_6 m4 i/o 6 io_l39p_6 io_l39p_6 m3 i/o 6 io_l40n_6 io_l40n_6 m2 i/o 6 io_l40p_6/ vref_6 io_l40p_6/ vref_6 m1 vref 6 vcco_6 vcco_6 m7 vcco 6 vcco_6 vcco_6 n7 vcco 6 vcco_6 vcco_6 p7 vcco 6 vcco_6 vcco_6 r3 vcco 6 vcco_6 vcco_6 r6 vcco 7 io io c2 i/o 7 io_l01n_7/ vrp_7 io_l01n_7/ vrp_7 c3 dci 7 io_l01p_7/ vrn_7 io_l01p_7/ vrn_7 c4 dci ta bl e 2 7 : fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type 7 io_l16n_7 io_l16n_7 d1 i/o 7 io_l16p_7/ vref_7 io_l16p_7/ vref_7 c1 vref 7 io_l17n_7 io_l17n_7 e4 i/o 7 io_l17p_7 io_l17p_7 d4 i/o 7 io_l19n_7/ vref_7 io_l19n_7/ vref_7 d3 vref 7 io_l19p_7 io_l19p_7 d2 i/o 7 io_l20n_7 io_l20n_7 f4 i/o 7 io_l20p_7 io_l20p_7 e3 i/o 7 io_l21n_7 io_l21n_7 e1 i/o 7 io_l21p_7 io_l21p_7 e2 i/o 7 io_l22n_7 io_l22n_7 g6 i/o 7 io_l22p_7 io_l22p_7 f5 i/o 7 io_l23n_7 io_l23n_7 f2 i/o 7 io_l23p_7 io_l23p_7 f3 i/o 7 io_l24n_7 io_l24n_7 h5 i/o 7 io_l24p_7 io_l24p_7 g5 i/o 7 n.c. ( ? ) io_l26n_7 g3 i/o 7 n.c. ( ? ) io_l26p_7 g4 i/o 7 io_l27n_7 io_l27n_7 g1 i/o 7 io_l27p_7/ vref_7 io_l27p_7/ vref_7 g2 vref 7 n.c. ( ? ) io_l28n_7 h1 i/o 7 n.c. ( ? ) io_l28p_7 h2 i/o 7 n.c. ( ? ) io_l29n_7 j4 i/o 7 n.c. ( ? ) io_l29p_7 h4 i/o 7 n.c. ( ? ) io_l31n_7 j5 i/o 7 n.c. ( ? ) io_l31p_7 j6 i/o 7 n.c. ( ? ) io_l32n_7 j1 i/o 7 n.c. ( ? ) io_l32p_7 j2 i/o 7 n.c. ( ? ) io_l33n_7 k5 i/o 7 n.c. ( ? ) io_l33p_7 k6 i/o 7 io_l34n_7 io_l34n_7 k3 i/o 7 io_l34p_7 io_l34p_7 k4 i/o 7 io_l35n_7 io_l35n_7 k1 i/o 7 io_l35p_7 io_l35p_7 k2 i/o 7 io_l38n_7 io_l38n_7 l5 i/o 7 io_l38p_7 io_l38p_7 l6 i/o 7 io_l39n_7 io_l39n_7 l3 i/o 7 io_l39p_7 io_l39p_7 l4 i/o 7 io_l40n_7/ vref_7 io_l40n_7/ vref_7 l1 vref 7 io_l40p_7 io_l40p_7 l2 i/o 7 vcco_7 vcco_7 h3 vcco 7 vcco_7 vcco_7 h6 vcco table 27: fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type
spartan-3 fpga family: pinout descriptions 54 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 7 vcco_7 vcco_7 j7 vcco 7 vcco_7 vcco_7 k7 vcco 7 vcco_7 vcco_7 l7 vcco n/a gnd gnd a1 gnd n/a gnd gnd a22 gnd n/a gnd gnd aa2 gnd n/a gnd gnd aa21 gnd n/a gnd gnd ab1 gnd n/a gnd gnd ab22 gnd n/a gnd gnd b2 gnd n/a gnd gnd b21 gnd n/a gnd gnd c9 gnd n/a gnd gnd c14 gnd n/a gnd gnd j3 gnd n/a gnd gnd j9 gnd n/a gnd gnd j10 gnd n/a gnd gnd j11 gnd n/a gnd gnd j12 gnd n/a gnd gnd j13 gnd n/a gnd gnd j14 gnd n/a gnd gnd j20 gnd n/a gnd gnd k9 gnd n/a gnd gnd k10 gnd n/a gnd gnd k11 gnd n/a gnd gnd k12 gnd n/a gnd gnd k13 gnd n/a gnd gnd k14 gnd n/a gnd gnd l9 gnd n/a gnd gnd l10 gnd n/a gnd gnd l11 gnd n/a gnd gnd l12 gnd n/a gnd gnd l13 gnd n/a gnd gnd l14 gnd n/a gnd gnd m9 gnd n/a gnd gnd m10 gnd n/a gnd gnd m11 gnd n/a gnd gnd m12 gnd n/a gnd gnd m13 gnd n/a gnd gnd m14 gnd n/a gnd gnd n9 gnd n/a gnd gnd n10 gnd n/a gnd gnd n11 gnd n/a gnd gnd n12 gnd n/a gnd gnd n13 gnd n/a gnd gnd n14 gnd ta bl e 2 7 : fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type n/a gnd gnd p3 gnd n/a gnd gnd p9 gnd n/a gnd gnd p10 gnd n/a gnd gnd p11 gnd n/a gnd gnd p12 gnd n/a gnd gnd p13 gnd n/a gnd gnd p14 gnd n/a gnd gnd p20 gnd n/a gnd gnd y9 gnd n/a gnd gnd y14 gnd n/a vccaux vccaux a6 vccaux n/a vccaux vccaux a17 vccaux n/a vccaux vccaux ab6 vccaux n/a vccaux vccaux ab17 vccaux n/a vccaux vccaux f1 vccaux n/a vccaux vccaux f22 vccaux n/a vccaux vccaux u1 vccaux n/a vccaux vccaux u22 vccaux n/a vccint vccint g7 vccint n/a vccint vccint g8 vccint n/a vccint vccint g15 vccint n/a vccint vccint g16 vccint n/a vccint vccint h7 vccint n/a vccint vccint h16 vccint n/a vccint vccint r7 vccint n/a vccint vccint r16 vccint n/a vccint vccint t7 vccint n/a vccint vccint t8 vccint n/a vccint vccint t15 vccint n/a vccint vccint t16 vccint vccaux cclk cclk aa22 config vccaux done done ab21 config vccaux hswap_en hswap_en b3 config vccaux m0 m0 ab2 config vccaux m1 m1 aa1 config vccaux m2 m2 ab3 config vccaux prog_b prog_b a2 config vccaux tck tck a21 jtag vccaux tdi tdi b1 jtag vccaux tdo tdo b22 jtag vccaux tms tms a20 jtag table 27: fg456 package pinout (continued) bank 3s400 pin name 3s1000 3s1500 pin name fg456 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 55 product specification 1-800-255-7778 r user i/os by bank ta bl e 2 8 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks for the xc3s400 in the fg456 package. similarly, ta bl e 2 9 shows how the avail- able user-i/o pins are distributed between the eight i/o banks for the xc3s1000 and xc3s1500 in the fg456 package. ta bl e 2 8 : user i/os per bank for xc3s400 in fg456 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 35 27 0 2 4 2 1 35 27 0 2 4 2 right 2 31 25 0 2 4 0 3 31 25 0 2 4 0 bottom 4 35 21 6 2 4 2 5 35 21 6 2 4 2 left 6 31 25 0 2 4 0 7 31 25 0 2 4 0 ta bl e 2 9 : user i/os per bank for xc3s1000 and xc3s1500 in fg456 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 40 31 0 2 5 2 1 40 31 0 2 5 2 right 2 43 37 0 2 4 0 3 43 37 0 2 4 0 bottom 4 41 26 6 2 5 2 5 40 25 6 2 5 2 left 6 43 37 0 2 4 0 7 43 37 0 2 4 0
spartan-3 fpga family: pinout descriptions 56 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg456 footprint left half of package (top view) xc3s400 (264 max. user i/o) 196 i/o: unrestricted, general-purpose user i/o 32 vref: user i/o or input voltage reference for bank 69 n.c.: unconnected pins for xc3s400 ( ? ) xc3s1000, xc3s1500 (333 max user i/o) 261 i/o: unrestricted, general-purpose user i/o 36 vref: user i/o or input voltage reference for bank 0 n.c.: no unconnected pins in this package all devices 12 dual: configuration pin, then possible user i/o 8 gclk: user i/o or global clock buffer input 16 dci: user i/o or reference resistor input for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 12 vccint: internal core voltage supply (+1.2v) 40 vcco: output voltage supply for bank 8 vccaux: auxiliary voltage supply (+2.5v) 52 gnd: ground figure 13: fg456 package footprint (top view) bank 5 bank 0 a b c d e f g h j k l m n p r t u v w y a a a b bank 7 bank 6 prog_b io vref_0 i/o l01p_0 vrn_0 i/o l09p_0 vccaux i/o l19p_0 i/o l24p_0 i/o l27p_0 i/o i/o l32p_0 gclk6 tdi hswap_ en i/o l01n_0 vrp_0 i/o l09n_0 i/o l15p_0 i/o l19n_0 i/o l24n_0 i/o l27n_0 i/o l29p_0 i/o l32n_0 gclk7 i/o l16p_7 vref_7 i/o i/o l01n_7 vrp_7 i/o l01p_7 vrn_7 i/o l06p_0 i/o l15n_0 io vref_0 vcco_0 gnd gnd gnd i/o l29n_0 i/o l31p_0 vref_0 i/o l16n_7 i/o l19p_7 i/o l19n_7 vref_7 i/o l17p_7 i/o l06n_0 i/o l10p_0 i/o l16p_0 i/o l22p_0 i/o i/o i/o l31n_0 i/o l21n_7 i/o l21p_7 i/o l20p_7 i/o l17n_7 io vref_0 i/o l10n_0 i/o l16n_0 i/o l22n_0 i/o l25p_0 i/o l28p_0 i/o l30p_0 vccaux i/o l23n_7 i/o l23p_7 i/o l20n_7 i/o l22p_7 i/o io vref_0 vcco_0 i/o l25n_0 i/o l28n_0 i/o l30n_0 i/o l27n_7 i/o l27p_7 vref_7 i/o l26n_7 i/o l26p_7 i/o l24p_7 i/o l22n_7 vccint vccint vcco_0 vcco_0 vcco_0 i/o l28n_7 i/o l28p_7 vcco_7 i/o l29p_7 i/o l24n_7 vcco_7 vccint i/o l32n_7 i/o l32p_7 gnd i/o l29n_7 i/o l31n_7 i/o l31p_7 vcco_7 i/o l35n_7 i/o l35p_7 i/o l34n_7 i/o l34p_7 i/o l33n_7 i/o l33p_7 vcco_7 i/o l40n_7 vref_7 i/o l40p_7 i/o l39n_7 i/o l39p_7 i/o l38n_7 i/o l38p_7 vcco_7 i/o l40p_6 vref_6 i/o l40n_6 i/o l39p_6 i/o l39n_6 i/o l38p_6 i/o l38n_6 vcco_6 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o l35p_6 i/o l35n_6 i/o l34p_6 i/o l34n_6 vref_6 i/o l33p_6 i/o l33n_6 vcco_6 i/o l32p_6 i/o l32n_6 gnd i/o l31p_6 i/o l31n_6 i/o l28p_6 vcco_6 i/o l29p_6 i/o l29n_6 vcco_6 i/o l26p_6 i/o l28n_6 vcco_6 vccint i/o l27p_6 i/o l27n_6 i/o l26n_6 i/o l23p_6 i/o l22p_6 i/o l22n_6 vccint vccint vcco_5 vcco_5 vcco_5 vccaux i/o l24p_6 i/o l24n_6 vref_6 i/o l23n_6 i/o l19p_6 io vref_5 i/o vcco_5 i/o i/o i/o i/o l21p_6 i/o l21n_6 i/o l20p_6 i/o l20n_6 i/o l19n_6 i/o l15p_5 i/o i/o l24p_5 i/o l27p_5 i/o i/o l31p_5 d5 i/o l17p_6 vref_6 i/o l17n_6 i/o l16p_6 i/o l16n_6 i/o l09p_5 i/o l15n_5 i/o l19p_5 vref_5 i/o l24n_5 i/o l27n_5 vref_5 i/o l29p_5 vref_5 i/o l31n_5 d4 i/o i/o l01p_6 vrn_6 i/o l01n_6 vrp_6 i/o l01n_5 rdwr_b i/o l09n_5 i/o l16p_5 i/o l19n_5 vcco_5 i/o l29n_5 i/o l32p_5 gclk2 m1 i/o l01p_5 cs_b i/o l06p_5 i/o l10p_5 vrn_5 i/o l16n_5 i/o l22p_5 i/o l25p_5 i/o l28p_5 d7 i/o l30p_5 i/o l32n_5 gclk3 gnd gnd gnd m0 m2 i/o l06n_5 i/o l10n_5 vrp_5 vccaux i/o l22n_5 ? ? ? ? ? ? ?? ? ?? ? ?? ? ? ? ?? ?? ??? ?? ?? ?? ??? ? i/o l25n_5 i/o l28n_5 d6 i/o l30n_5 io vref_5 ds099-4_11a_030203 10 34 12 5 6 789 11
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 57 product specification 1-800-255-7778 r right half of package (top view) 12 13 14 15 16 17 18 19 20 21 22 bank 1 bank 4 a b c d e f g h j k l m n p r t u v w y a a a b bank 2 bank 3 i/o i/o l30n_1 i/o l28n_1 i/o l25p_1 i/o l22n_1 vccaux i/o l10n_1 vref_1 i/o l06n_1 vref_1 tms tck tdo gnd i/o l32n_1 gclk5 i/o l30p_1 i/o l28p_1 i/o l25n_1 i/o i/o l16n_1 i/o l10p_1 i/o l06p_1 i/o l01p_1 vrn_1 gnd i/o l32p_1 gclk4 i/o l29n_1 gnd vcco_1 i/o l19n_1 i/o l16p_1 i/o l09n_1 i/o l01n_1 vrp_1 i/o l01n_2 vrp_2 i/o l01p_2 vrn_2 i/o i/o l31n_1 vref_1 i/o l29p_1 i/o l27n_1 i/o l24n_1 i/o l19p_1 i/o l15n_1 i/o l09p_1 i/o l16p_2 i/o l16n_2 i/o l17n_2 i/o l17p_2 vref_2 i/o l31p_1 io vref_1 i/o l27p_1 i/o l24p_1 i/o i/o l15p_1 i/o l19n_2 i/o l20n_2 i/o l20p_2 i/o l21n_2 i/o l21p_2 i/o i/o io vref_1 vcco_1 i/o i/o i/o l19p_2 i/o l23n_2 vref_2 i/o l24n_2 i/o l24p_2 vccaux vcco_1 vcco_1 vcco_1 vccint vccint i/o l22n_2 i/o l22p_2 i/o l23p_2 i/o l26n_2 i/o l27n_2 i/o l27p_2 vccint vcco_2 i/o l28n_2 i/o l26p_2 vcco_2 i/o l29n_2 i/o l29p_2 gnd gnd gnd vcco_2 i/o l28p_2 i/o l31n_2 i/o l31p_2 gnd i/o l32n_2 i/o l32p_2 gnd gnd gnd vcco_2 i/o l33n_2 i/o l33p_2 i/o l34n_2 vref_2 i/o l34p_2 i/o l35n_2 i/o l35p_2 gnd gnd gnd vcco_2 i/o l38n_2 i/o l38p_2 i/o l39n_2 i/o l39p_2 i/o l40n_2 i/o l40p_2 vref_2 gnd gnd gnd vcco_3 i/o l38p_3 i/o l38n_3 i/o l39p_3 i/o l39n_3 i/o l40p_3 i/o l40n_3 vref_3 gnd gnd gnd vcco_3 i/o l33p_3 i/o l33n_3 i/o l34p_3 vref_3 i/o l34n_3 i/o l35p_3 i/o l35n_3 gnd gnd gnd vcco_3 i/o l31p_3 i/o l31n_3 i/o l29n_3 gnd i/o l32p_3 i/o l32n_3 vccint vcco_3 i/o l24n_3 i/o l29p_3 vcco_3 i/o l28p_3 i/o l28n_3 vcco_4 vcco_4 vcco_4 vccint vccint i/o l22n_3 i/o l24p_3 i/o l26p_3 i/o l26n_3 i/o l27p_3 i/o l27n_3 i/o l30n_4 d2 i/o l28n_4 i/o l25n_4 vcco_4 i/o i/o i/o l22p_3 i/o l20n_3 i/o l23p_3 vref_3 i/o l23n_3 vccaux i/o l30p_4 d3 i/o l28p_4 i/o l25p_4 i/o l22n_4 vref_4 i/o l16n_4 i/o l10n_4 io vref_4 i/o l17n_3 i/o l20p_3 i/o l21p_3 i/o l21n_3 i/o l31n_4 init_b i/o i/o i/o l22p_4 i/o l16p_4 i/o l10p_4 i/o l06n_4 vref_4 i/o l17p_3 vref_3 i/o l19p_3 i/o l19n_3 i/o l16n_3 i/o l31p_4 dout busy i/o l29n_4 gnd vcco_4 io vref_4 i/o l15n_4 i/o l06p_4 i/o l01p_3 vrn_3 i/o l01n_3 vrp_3 i/o i/o l16p_3 i/o l32n_4 gclk1 i/o l29p_4 i/o l27n_4 din d0 i/o l24n_4 i/o l19n_4 i/o l15p_4 i/o l09n_4 i/o l05n_4 i/o l01n_4 vrp_4 gnd cclk i/o l32p_4 gclk0 io vref_4 i/o l27p_4 d1 i/o l24p_4 i/o l19p_4 vccaux i/o l09p_4 i/o l05p_4 i/o l01p_4 vrn_4 done gnd ds099-4_11b_030503 l22p_1 ? ? ? ? ? ? ?? ? ? ??? ?? ?? ?? ??? ?? ??? ?? ? ? ?? ??
spartan-3 fpga family: pinout descriptions 58 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg676: 676-lead fine -pitch ball grid array the 676-lead fine-pitch ball grid array package, fg676, supports three different spartan-3 devices, including the xc3s1000, the xc3s1500, and the xc3s2000. all three have nearly identical footprints but are slightly different due to unconnected pins on the xc3s1000 and xc3s1500. for example, because the xc3s1000 has fewer i/o pins, this device has 98 unconnected pins on the fg676 package, labeled as ?n.c.? in ta bl e 3 0 and figure 14 , these uncon- nected pins are indicated with a black diamond symbol ( ? ). the xc3s1500, however, has only two unconnected pins, also labeled ?n.c.? in the pinout table but indicated with a black square symbol ( ? ). all the package pins appear in ta bl e 3 0 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. if there is a difference between the xc1000, xc3s1500 and xc3s2000 pinouts, then that difference is highlighted in ta bl e 3 0 . if the table entry is shaded grey, then there is an unconnected pin on either the xc3s1000 or xc3s1500 that maps to a user-i/o pin on the xc3s2000. if the table entry is shaded tan, then the unconnected pin on either the xc3s1000 or xc3s1500 maps to a vref-type pin on the xc3s2000. if the other vref pins in the bank all connect to a voltage reference to support a special i/o standard, then also connect the n.c. pin on the xc3s1000 or xc3s1500 to the same vref voltage. this provides maximum flexibil- ity as you could potentially migrate a design from the xc3s1000 through to the xc3s2000 fpga without chang- ing the printed circuit board. pinout table ta bl e 3 0 : fg676 package pinout bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 0 io io io a3 i/o 0 io io io a5 i/o 0 io io io a6 i/o 0 io io io c4 i/o 0 n.c. ( ? ) io io c8 i/o 0 io io io c12 i/o 0 io io io e13 i/o 0 io io io h11 i/o 0 io io io h12 i/o 0 io/vref_0 io/vref_0 io/vref_0 b3 vref 0 io/vref_0 io/vref_0 io/vref_0 f7 vref 0 io/vref_0 io/vref_0 io/vref_0 g10 vref 0 io_l01n_0/ vrp_0 io_l01n_0/ vrp_0 io_l01n_0/ vrp_0 e5 dci 0 io_l01p_0/ vrn_0 io_l01p_0/ vrn_0 io_l01p_0/ vrn_0 d5 dci 0 io_l05n_0 io_l05n_0 io_l05n_0 b4 i/o 0 io_l05p_0/ vref_0 io_l05p_0/ vref_0 io_l05p_0/ vref_0 a4 vref 0 io_l06n_0 io_l06n_0 io_l06n_0 c5 i/o 0 io_l06p_0 io_l06p_0 io_l06p_0 b5 i/o 0 io_l07n_0 io_l07n_0 io_l07n_0 e6 i/o 0 io_l07p_0 io_l07p_0 io_l07p_0 d6 i/o 0 io_l08n_0 io_l08n_0 io_l08n_0 c6 i/o 0 io_l08p_0 io_l08p_0 io_l08p_0 b6 i/o 0 io_l09n_0 io_l09n_0 io_l09n_0 e7 i/o 0 io_l09p_0 io_l09p_0 io_l09p_0 d7 i/o 0 io_l10n_0 io_l10n_0 io_l10n_0 b7 i/o 0 io_l10p_0 io_l10p_0 io_l10p_0 a7 i/o 0 n.c. ( ? ) io_l11n_0 io_l11n_0 g8 i/o 0 n.c. ( ? ) io_l11p_0 io_l11p_0 f8 i/o 0 n.c. ( ? ) io_l12n_0 io_l12n_0 e8 i/o 0 n.c. ( ? ) io_l12p_0 io_l12p_0 d8 i/o 0 io_l15n_0 io_l15n_0 io_l15n_0 b8 i/o 0 io_l15p_0 io_l15p_0 io_l15p_0 a8 i/o 0 io_l16n_0 io_l16n_0 io_l16n_0 g9 i/o 0 io_l16p_0 io_l16p_0 io_l16p_0 f9 i/o 0 n.c. ( ? ) io_l17n_0 io_l17n_0 e9 i/o 0 n.c. ( ? ) io_l17p_0 io_l17p_0 d9 i/o 0 n.c. ( ? ) io_l18n_0 io_l18n_0 c9 i/o 0 n.c. ( ? ) io_l18p_0 io_l18p_0 b9 i/o 0 io_l19n_0 io_l19n_0 io_l19n_0 f10 i/o 0 io_l19p_0 io_l19p_0 io_l19p_0 e10 i/o 0 io_l22n_0 io_l22n_0 io_l22n_0 d10 i/o 0 io_l22p_0 io_l22p_0 io_l22p_0 c10 i/o 0 n.c. ( ? ) io_l23n_0 io_l23n_0 b10 i/o 0 n.c. ( ? ) io_l23p_0 io_l23p_0 a10 i/o 0 io_l24n_0 io_l24n_0 io_l24n_0 g11 i/o 0 io_l24p_0 io_l24p_0 io_l24p_0 f11 i/o 0 io_l25n_0 io_l25n_0 io_l25n_0 e11 i/o 0 io_l25p_0 io_l25p_0 io_l25p_0 d11 i/o 0 n.c. ( ? ) io_l26n_0 io_l26n_0 b11 i/o 0 n.c. ( ? ) io_l26p_0/ vref_0 io_l26p_0/ vref_0 a11 vref 0 io_l27n_0 io_l27n_0 io_l27n_0 g12 i/o 0 io_l27p_0 io_l27p_0 io_l27p_0 h13 i/o 0 io_l28n_0 io_l28n_0 io_l28n_0 f12 i/o 0 io_l28p_0 io_l28p_0 io_l28p_0 e12 i/o 0 io_l29n_0 io_l29n_0 io_l29n_0 b12 i/o 0 io_l29p_0 io_l29p_0 io_l29p_0 a12 i/o table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 59 product specification 1-800-255-7778 r 0 io_l30n_0 io_l30n_0 io_l30n_0 g13 i/o 0 io_l30p_0 io_l30p_0 io_l30p_0 f13 i/o 0 io_l31n_0 io_l31n_0 io_l31n_0 d13 i/o 0 io_l31p_0/ vref_0 io_l31p_0/ vref_0 io_l31p_0/ vref_0 c13 vref 0 io_l32n_0/ gclk7 io_l32n_0/ gclk7 io_l32n_0/ gclk7 b13 gclk 0 io_l32p_0/ gclk6 io_l32p_0/ gclk6 io_l32p_0/ gclk6 a13 gclk 0 vcco_0 vcco_0 vcco_0 c7 vcco 0 vcco_0 vcco_0 vcco_0 c11 vcco 0 vcco_0 vcco_0 vcco_0 h9 vcco 0 vcco_0 vcco_0 vcco_0 h10 vcco 0 vcco_0 vcco_0 vcco_0 j11 vcco 0 vcco_0 vcco_0 vcco_0 j12 vcco 0 vcco_0 vcco_0 vcco_0 j13 vcco 0 vcco_0 vcco_0 vcco_0 k13 vcco 1 io io io a14 i/o 1 io io io a22 i/o 1 io io io a23 i/o 1 io io io d16 i/o 1 io io io e18 i/o 1 io io io f14 i/o 1 io io io f20 i/o 1 io io io g19 i/o 1 io/vref_1 io/vref_1 io/vref_1 c15 vref 1 io/vref_1 io/vref_1 io/vref_1 c17 vref 1 n.c. ( ? ) io/vref_1 io/vref_1 d18 vref 1 io_l01n_1/ vrp_1 io_l01n_1/ vrp_1 io_l01n_1/ vrp_1 d22 dci 1 io_l01p_1/ vrn_1 io_l01p_1/ vrn_1 io_l01p_1/ vrn_1 e22 dci 1 io_l04n_1 io_l04n_1 io_l04n_1 b23 i/o 1 io_l04p_1 io_l04p_1 io_l04p_1 c23 i/o 1 io_l05n_1 io_l05n_1 io_l05n_1 e21 i/o 1 io_l05p_1 io_l05p_1 io_l05p_1 f21 i/o 1 io_l06n_1/ vref_1 io_l06n_1/ vref_1 io_l06n_1/ vref_1 b22 vref 1 io_l06p_1 io_l06p_1 io_l06p_1 c22 i/o 1 io_l07n_1 io_l07n_1 io_l07n_1 c21 i/o 1 io_l07p_1 io_l07p_1 io_l07p_1 d21 i/o 1 io_l08n_1 io_l08n_1 io_l08n_1 a21 i/o 1 io_l08p_1 io_l08p_1 io_l08p_1 b21 i/o 1 io_l09n_1 io_l09n_1 io_l09n_1 d20 i/o 1 io_l09p_1 io_l09p_1 io_l09p_1 e20 i/o 1 io_l10n_1/ vref_1 io_l10n_1/ vref_1 io_l10n_1/ vref_1 a20 vref ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 1 io_l10p_1 io_l10p_1 io_l10p_1 b20 i/o 1 n.c. ( ? ) io_l11n_1 io_l11n_1 e19 i/o 1 n.c. ( ? ) io_l11p_1 io_l11p_1 f19 i/o 1 n.c. ( ? ) io_l12n_1 io_l12n_1 c19 i/o 1 n.c. ( ? ) io_l12p_1 io_l12p_1 d19 i/o 1 io_l15n_1 io_l15n_1 io_l15n_1 a19 i/o 1 io_l15p_1 io_l15p_1 io_l15p_1 b19 i/o 1 io_l16n_1 io_l16n_1 io_l16n_1 f18 i/o 1 io_l16p_1 io_l16p_1 io_l16p_1 g18 i/o 1 n.c. ( ? ) io_l18n_1 io_l18n_1 b18 i/o 1 n.c. ( ? ) io_l18p_1 io_l18p_1 c18 i/o 1 io_l19n_1 io_l19n_1 io_l19n_1 f17 i/o 1 io_l19p_1 io_l19p_1 io_l19p_1 g17 i/o 1 io_l22n_1 io_l22n_1 io_l22n_1 d17 i/o 1 io_l22p_1 io_l22p_1 io_l22p_1 e17 i/o 1 n.c. ( ? ) io_l23n_1 io_l23n_1 a17 i/o 1 n.c. ( ? ) io_l23p_1 io_l23p_1 b17 i/o 1 io_l24n_1 io_l24n_1 io_l24n_1 g16 i/o 1 io_l24p_1 io_l24p_1 io_l24p_1 h16 i/o 1 io_l25n_1 io_l25n_1 io_l25n_1 e16 i/o 1 io_l25p_1 io_l25p_1 io_l25p_1 f16 i/o 1 n.c. ( ? ) io_l26n_1 io_l26n_1 a16 i/o 1 n.c. ( ? ) io_l26p_1 io_l26p_1 b16 i/o 1 io_l27n_1 io_l27n_1 io_l27n_1 g15 i/o 1 io_l27p_1 io_l27p_1 io_l27p_1 h15 i/o 1 io_l28n_1 io_l28n_1 io_l28n_1 e15 i/o 1 io_l28p_1 io_l28p_1 io_l28p_1 f15 i/o 1 io_l29n_1 io_l29n_1 io_l29n_1 a15 i/o 1 io_l29p_1 io_l29p_1 io_l29p_1 b15 i/o 1 io_l30n_1 io_l30n_1 io_l30n_1 g14 i/o 1 io_l30p_1 io_l30p_1 io_l30p_1 h14 i/o 1 io_l31n_1/ vref_1 io_l31n_1/ vref_1 io_l31n_1/ vref_1 d14 vref 1 io_l31p_1 io_l31p_1 io_l31p_1 e14 i/o 1 io_l32n_1/ gclk5 io_l32n_1/ gclk5 io_l32n_1/ gclk5 b14 gclk 1 io_l32p_1/ gclk4 io_l32p_1/ gclk4 io_l32p_1/ gclk4 c14 gclk 1 vcco_1 vcco_1 vcco_1 c16 vcco 1 vcco_1 vcco_1 vcco_1 c20 vcco 1 vcco_1 vcco_1 vcco_1 h17 vcco 1 vcco_1 vcco_1 vcco_1 h18 vcco 1 vcco_1 vcco_1 vcco_1 j14 vcco 1 vcco_1 vcco_1 vcco_1 j15 vcco 1 vcco_1 vcco_1 vcco_1 j16 vcco table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions 60 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 1 vcco_1 vcco_1 vcco_1 k14 vcco 2 n.c. ( ? ) n.c. ( ? ) io f22 i/o 2 io_l01n_2/ vrp_2 io_l01n_2/ vrp_2 io_l01n_2/ vrp_2 c25 dci 2 io_l01p_2/ vrn_2 io_l01p_2/ vrn_2 io_l01p_2/ vrn_2 c26 dci 2 io_l02n_2 io_l02n_2 io_l02n_2 e23 i/o 2 io_l02p_2 io_l02p_2 io_l02p_2 e24 i/o 2 io_l03n_2/ vref_2 io_l03n_2/ vref_2 io_l03n_2/ vref_2 d25 vref 2 io_l03p_2 io_l03p_2 io_l03p_2 d26 i/o 2 n.c. ( ? ) io_l05n_2 io_l05n_2 e25 i/o 2 n.c. ( ? ) io_l05p_2 io_l05p_2 e26 i/o 2 n.c. ( ? ) io_l06n_2 io_l06n_2 g20 i/o 2 n.c. ( ? ) io_l06p_2 io_l06p_2 g21 i/o 2 n.c. ( ? ) io_l07n_2 io_l07n_2 f23 i/o 2 n.c. ( ? ) io_l07p_2 io_l07p_2 f24 i/o 2 n.c. ( ? ) io_l08n_2 io_l08n_2 g22 i/o 2 n.c. ( ? ) io_l08p_2 io_l08p_2 g23 i/o 2 n.c. ( ? ) io_l09n_2/ vref_2 io_l09n_2/ vref_2 f25 vref 2 n.c. ( ? ) io_l09p_2 io_l09p_2 f26 i/o 2 n.c. ( ? ) io_l10n_2 io_l10n_2 g25 i/o 2 n.c. ( ? ) io_l10p_2 io_l10p_2 g26 i/o 2 io_l14n_2 io_l14n_2 io_l14n_2 h20 i/o 2 io_l14p_2 io_l14p_2 io_l14p_2 h21 i/o 2 io_l16n_2 io_l16n_2 io_l16n_2 h22 i/o 2 io_l16p_2 io_l16p_2 io_l16p_2 j21 i/o 2 io_l17n_2 io_l17n_2 io_l17n_2 h23 i/o 2 io_l17p_2/ vref_2 io_l17p_2/ vref_2 io_l17p_2/ vref_2 h24 vref 2 io_l19n_2 io_l19n_2 io_l19n_2 h25 i/o 2 io_l19p_2 io_l19p_2 io_l19p_2 h26 i/o 2 io_l20n_2 io_l20n_2 io_l20n_2 j20 i/o 2 io_l20p_2 io_l20p_2 io_l20p_2 k20 i/o 2 io_l21n_2 io_l21n_2 io_l21n_2 j22 i/o 2 io_l21p_2 io_l21p_2 io_l21p_2 j23 i/o 2 io_l22n_2 io_l22n_2 io_l22n_2 j24 i/o 2 io_l22p_2 io_l22p_2 io_l22p_2 j25 i/o 2 io_l23n_2/ vref_2 io_l23n_2/ vref_2 io_l23n_2/ vref_2 k21 vref 2 io_l23p_2 io_l23p_2 io_l23p_2 k22 i/o 2 io_l24n_2 io_l24n_2 io_l24n_2 k23 i/o 2 io_l24p_2 io_l24p_2 io_l24p_2 k24 i/o 2 io_l26n_2 io_l26n_2 io_l26n_2 k25 i/o 2 io_l26p_2 io_l26p_2 io_l26p_2 k26 i/o 2 io_l27n_2 io_l27n_2 io_l27n_2 l19 i/o ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 2 io_l27p_2 io_l27p_2 io_l27p_2 l20 i/o 2 io_l28n_2 io_l28n_2 io_l28n_2 l21 i/o 2 io_l28p_2 io_l28p_2 io_l28p_2 l22 i/o 2 io_l29n_2 io_l29n_2 io_l29n_2 l25 i/o 2 io_l29p_2 io_l29p_2 io_l29p_2 l26 i/o 2 io_l31n_2 io_l31n_2 io_l31n_2 m19 i/o 2 io_l31p_2 io_l31p_2 io_l31p_2 m20 i/o 2 io_l32n_2 io_l32n_2 io_l32n_2 m21 i/o 2 io_l32p_2 io_l32p_2 io_l32p_2 m22 i/o 2 io_l33n_2 io_l33n_2 io_l33n_2 l23 i/o 2 io_l33p_2 io_l33p_2 io_l33p_2 m24 i/o 2 io_l34n_2/ vref_2 io_l34n_2/ vref_2 io_l34n_2/ vref_2 m25 vref 2 io_l34p_2 io_l34p_2 io_l34p_2 m26 i/o 2 io_l35n_2 io_l35n_2 io_l35n_2 n19 i/o 2 io_l35p_2 io_l35p_2 io_l35p_2 n20 i/o 2 io_l38n_2 io_l38n_2 io_l38n_2 n21 i/o 2 io_l38p_2 io_l38p_2 io_l38p_2 n22 i/o 2 io_l39n_2 io_l39n_2 io_l39n_2 n23 i/o 2 io_l39p_2 io_l39p_2 io_l39p_2 n24 i/o 2 io_l40n_2 io_l40n_2 io_l40n_2 n25 i/o 2 io_l40p_2/ vref_2 io_l40p_2/ vref_2 io_l40p_2/ vref_2 n26 vref 2 vcco_2 vcco_2 vcco_2 g24 vcco 2 vcco_2 vcco_2 vcco_2 j19 vcco 2 vcco_2 vcco_2 vcco_2 k19 vcco 2 vcco_2 vcco_2 vcco_2 l18 vcco 2 vcco_2 vcco_2 vcco_2 l24 vcco 2 vcco_2 vcco_2 vcco_2 m18 vcco 2 vcco_2 vcco_2 vcco_2 n17 vcco 2 vcco_2 vcco_2 vcco_2 n18 vcco 3 io_l01n_3/ vrp_3 io_l01n_3/ vrp_3 io_l01n_3/ vrp_3 aa22 dci 3 io_l01p_3/ vrn_3 io_l01p_3/ vrn_3 io_l01p_3/ vrn_3 aa21 dci 3 io_l02n_3/ vref_3 io_l02n_3/ vref_3 io_l02n_3/ vref_3 ab24 vref 3 io_l02p_3 io_l02p_3 io_l02p_3 ab23 i/o 3 io_l03n_3 io_l03n_3 io_l03n_3 ac26 i/o 3 io_l03p_3 io_l03p_3 io_l03p_3 ac25 i/o 3 n.c. ( ? ) io_l05n_3 io_l05n_3 y21 i/o 3 n.c. ( ? ) io_l05p_3 io_l05p_3 y20 i/o 3 n.c. ( ? ) io_l06n_3 io_l06n_3 ab26 i/o 3 n.c. ( ? ) io_l06p_3 io_l06p_3 ab25 i/o 3 n.c. ( ? ) io_l07n_3 io_l07n_3 aa24 i/o 3 n.c. ( ? ) io_l07p_3 io_l07p_3 aa23 i/o 3 n.c. ( ? ) io_l08n_3 io_l08n_3 y23 i/o table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 61 product specification 1-800-255-7778 r 3 n.c. ( ? ) io_l08p_3 io_l08p_3 y22 i/o 3 n.c. ( ? ) io_l09n_3 io_l09n_3 aa26 i/o 3 n.c. ( ? ) io_l09p_3/ vref_3 io_l09p_3/ vref_3 aa25 vref 3 n.c. ( ? ) io_l10n_3 io_l10n_3 w21 i/o 3 n.c. ( ? ) io_l10p_3 io_l10p_3 w20 i/o 3 io_l14n_3 io_l14n_3 io_l14n_3 y26 i/o 3 io_l14p_3 io_l14p_3 io_l14p_3 y25 i/o 3 io_l16n_3 io_l16n_3 io_l16n_3 v21 i/o 3 io_l16p_3 io_l16p_3 io_l16p_3 w22 i/o 3 io_l17n_3 io_l17n_3 io_l17n_3 w24 i/o 3 io_l17p_3/ vref_3 io_l17p_3/ vref_3 io_l17p_3/ vref_3 w23 vref 3 io_l19n_3 io_l19n_3 io_l19n_3 w26 i/o 3 io_l19p_3 io_l19p_3 io_l19p_3 w25 i/o 3 io_l20n_3 io_l20n_3 io_l20n_3 u20 i/o 3 io_l20p_3 io_l20p_3 io_l20p_3 v20 i/o 3 io_l21n_3 io_l21n_3 io_l21n_3 v23 i/o 3 io_l21p_3 io_l21p_3 io_l21p_3 v22 i/o 3 io_l22n_3 io_l22n_3 io_l22n_3 v25 i/o 3 io_l22p_3 io_l22p_3 io_l22p_3 v24 i/o 3 io_l23n_3 io_l23n_3 io_l23n_3 u22 i/o 3 io_l23p_3/ vref_3 io_l23p_3/ vref_3 io_l23p_3/ vref_3 u21 vref 3 io_l24n_3 io_l24n_3 io_l24n_3 u24 i/o 3 io_l24p_3 io_l24p_3 io_l24p_3 u23 i/o 3 io_l26n_3 io_l26n_3 io_l26n_3 u26 i/o 3 io_l26p_3 io_l26p_3 io_l26p_3 u25 i/o 3 io_l27n_3 io_l27n_3 io_l27n_3 t20 i/o 3 io_l27p_3 io_l27p_3 io_l27p_3 t19 i/o 3 io_l28n_3 io_l28n_3 io_l28n_3 t22 i/o 3 io_l28p_3 io_l28p_3 io_l28p_3 t21 i/o 3 io_l29n_3 io_l29n_3 io_l29n_3 t26 i/o 3 io_l29p_3 io_l29p_3 io_l29p_3 t25 i/o 3 io_l31n_3 io_l31n_3 io_l31n_3 r20 i/o 3 io_l31p_3 io_l31p_3 io_l31p_3 r19 i/o 3 io_l32n_3 io_l32n_3 io_l32n_3 r22 i/o 3 io_l32p_3 io_l32p_3 io_l32p_3 r21 i/o 3 io_l33n_3 io_l33n_3 io_l33n_3 r24 i/o 3 io_l33p_3 io_l33p_3 io_l33p_3 t23 i/o 3 io_l34n_3 io_l34n_3 io_l34n_3 r26 i/o 3 io_l34p_3/ vref_3 io_l34p_3/ vref_3 io_l34p_3/ vref_3 r25 vref 3 io_l35n_3 io_l35n_3 io_l35n_3 p20 i/o 3 io_l35p_3 io_l35p_3 io_l35p_3 p19 i/o 3 io_l38n_3 io_l38n_3 io_l38n_3 p22 i/o ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 3 io_l38p_3 io_l38p_3 io_l38p_3 p21 i/o 3 io_l39n_3 io_l39n_3 io_l39n_3 p24 i/o 3 io_l39p_3 io_l39p_3 io_l39p_3 p23 i/o 3 io_l40n_3/ vref_3 io_l40n_3/ vref_3 io_l40n_3/ vref_3 p26 vref 3 io_l40p_3 io_l40p_3 io_l40p_3 p25 i/o 3 vcco_3 vcco_3 vcco_3 p17 vcco 3 vcco_3 vcco_3 vcco_3 p18 vcco 3 vcco_3 vcco_3 vcco_3 r18 vcco 3 vcco_3 vcco_3 vcco_3 t18 vcco 3 vcco_3 vcco_3 vcco_3 t24 vcco 3 vcco_3 vcco_3 vcco_3 u19 vcco 3 vcco_3 vcco_3 vcco_3 v19 vcco 3 vcco_3 vcco_3 vcco_3 y24 vcco 4 io io io aa20 i/o 4 io io io ad15 i/o 4 n.c. ( ? ) io io ad19 i/o 4 io io io ad23 i/o 4 io io io af21 i/o 4 io io io af22 i/o 4 io io io w15 i/o 4 io io io w16 i/o 4 io/vref_4 io/vref_4 io/vref_4 ab14 vref 4 io/vref_4 io/vref_4 io/vref_4 ad25 vref 4 io/vref_4 io/vref_4 io/vref_4 y17 vref 4 io_l01n_4/ vrp_4 io_l01n_4/ vrp_4 io_l01n_4/ vrp_4 ab22 dci 4 io_l01p_4/ vrn_4 io_l01p_4/ vrn_4 io_l01p_4/ vrn_4 ac22 dci 4 io_l04n_4 io_l04n_4 io_l04n_4 ae24 i/o 4 io_l04p_4 io_l04p_4 io_l04p_4 af24 i/o 4 io_l05n_4 io_l05n_4 io_l05n_4 ae23 i/o 4 io_l05p_4 io_l05p_4 io_l05p_4 af23 i/o 4 io_l06n_4/ vref_4 io_l06n_4/ vref_4 io_l06n_4/ vref_4 ad22 vref 4 io_l06p_4 io_l06p_4 io_l06p_4 ae22 i/o 4 io_l07n_4 io_l07n_4 io_l07n_4 ab21 i/o 4 io_l07p_4 io_l07p_4 io_l07p_4 ac21 i/o 4 io_l08n_4 io_l08n_4 io_l08n_4 ad21 i/o 4 io_l08p_4 io_l08p_4 io_l08p_4 ae21 i/o 4 io_l09n_4 io_l09n_4 io_l09n_4 ab20 i/o 4 io_l09p_4 io_l09p_4 io_l09p_4 ac20 i/o 4 io_l10n_4 io_l10n_4 io_l10n_4 ae20 i/o 4 io_l10p_4 io_l10p_4 io_l10p_4 af20 i/o 4 n.c. ( ? ) io_l11n_4 io_l11n_4 y19 i/o 4 n.c. ( ? ) io_l11p_4 io_l11p_4 aa19 i/o table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions 62 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 4 n.c. ( ? ) io_l12n_4 io_l12n_4 ab19 i/o 4 n.c. ( ? ) io_l12p_4 io_l12p_4 ac19 i/o 4 io_l15n_4 io_l15n_4 io_l15n_4 ae19 i/o 4 io_l15p_4 io_l15p_4 io_l15p_4 af19 i/o 4 io_l16n_4 io_l16n_4 io_l16n_4 y18 i/o 4 io_l16p_4 io_l16p_4 io_l16p_4 aa18 i/o 4 n.c. ( ? ) io_l17n_4 io_l17n_4 ab18 i/o 4 n.c. ( ? ) io_l17p_4 io_l17p_4 ac18 i/o 4 n.c. ( ? ) io_l18n_4 io_l18n_4 ad18 i/o 4 n.c. ( ? ) io_l18p_4 io_l18p_4 ae18 i/o 4 io_l19n_4 io_l19n_4 io_l19n_4 ac17 i/o 4 io_l19p_4 io_l19p_4 io_l19p_4 aa17 i/o 4 io_l22n_4/ vref_4 io_l22n_4/ vref_4 io_l22n_4/ vref_4 ad17 vref 4 io_l22p_4 io_l22p_4 io_l22p_4 ab17 i/o 4 n.c. ( ? ) io_l23n_4 io_l23n_4 ae17 i/o 4 n.c. ( ? ) io_l23p_4 io_l23p_4 af17 i/o 4 io_l24n_4 io_l24n_4 io_l24n_4 y16 i/o 4 io_l24p_4 io_l24p_4 io_l24p_4 aa16 i/o 4 io_l25n_4 io_l25n_4 io_l25n_4 ab16 i/o 4 io_l25p_4 io_l25p_4 io_l25p_4 ac16 i/o 4 n.c. ( ? ) io_l26n_4 io_l26n_4 ae16 i/o 4 n.c. ( ? ) io_l26p_4/ vref_4 io_l26p_4/ vref_4 af16 vref 4 io_l27n_4/ din/d0 io_l27n_4/ din/d0 io_l27n_4/ din/d0 y15 dual 4 io_l27p_4/ d1 io_l27p_4/ d1 io_l27p_4/ d1 w14 dual 4 io_l28n_4 io_l28n_4 io_l28n_4 aa15 i/o 4 io_l28p_4 io_l28p_4 io_l28p_4 ab15 i/o 4 io_l29n_4 io_l29n_4 io_l29n_4 ae15 i/o 4 io_l29p_4 io_l29p_4 io_l29p_4 af15 i/o 4 io_l30n_4/ d2 io_l30n_4/ d2 io_l30n_4/ d2 y14 dual 4 io_l30p_4/ d3 io_l30p_4/ d3 io_l30p_4/ d3 aa14 dual 4 io_l31n_4/ init_b io_l31n_4/ init_b io_l31n_4/ init_b ac14 dual 4 io_l31p_4/ dout/busy io_l31p_4/ dout/busy io_l31p_4/ dout/busy ad14 dual 4 io_l32n_4/ gclk1 io_l32n_4/ gclk1 io_l32n_4/ gclk1 ae14 gclk 4 io_l32p_4/ gclk0 io_l32p_4/ gclk0 io_l32p_4/ gclk0 af14 gclk 4 vcco_4 vcco_4 vcco_4 ad16 vcco 4 vcco_4 vcco_4 vcco_4 ad20 vcco 4 vcco_4 vcco_4 vcco_4 u14 vcco 4 vcco_4 vcco_4 vcco_4 v14 vcco ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 4 vcco_4 vcco_4 vcco_4 v15 vcco 4 vcco_4 vcco_4 vcco_4 v16 vcco 4 vcco_4 vcco_4 vcco_4 w17 vcco 4 vcco_4 vcco_4 vcco_4 w18 vcco 5 io io io aa7 i/o 5 io io io aa13 i/o 5 io io io ab9 i/o 5 n.c. ( ? ) io io ac9 i/o 5 io io io ac11 i/o 5 io io io ad10 i/o 5 io io io ad12 i/o 5 io io io af4 i/o 5 io io io y8 i/o 5 io/vref_5 io/vref_5 io/vref_5 af5 vref 5 io/vref_5 io/vref_5 io/vref_5 af13 vref 5 io_l01n_5/ rdwr_b io_l01n_5/ rdwr_b io_l01n_5/ rdwr_b ac5 dual 5 io_l01p_5/ cs_b io_l01p_5/ cs_b io_l01p_5/ cs_b ab5 dual 5 io_l04n_5 io_l04n_5 io_l04n_5 ae4 i/o 5 io_l04p_5 io_l04p_5 io_l04p_5 ad4 i/o 5 io_l05n_5 io_l05n_5 io_l05n_5 ab6 i/o 5 io_l05p_5 io_l05p_5 io_l05p_5 aa6 i/o 5 io_l06n_5 io_l06n_5 io_l06n_5 ae5 i/o 5 io_l06p_5 io_l06p_5 io_l06p_5 ad5 i/o 5 io_l07n_5 io_l07n_5 io_l07n_5 ad6 i/o 5 io_l07p_5 io_l07p_5 io_l07p_5 ac6 i/o 5 io_l08n_5 io_l08n_5 io_l08n_5 af6 i/o 5 io_l08p_5 io_l08p_5 io_l08p_5 ae6 i/o 5 io_l09n_5 io_l09n_5 io_l09n_5 ac7 i/o 5 io_l09p_5 io_l09p_5 io_l09p_5 ab7 i/o 5 io_l10n_5/ vrp_5 io_l10n_5/ vrp_5 io_l10n_5/ vrp_5 af7 dci 5 io_l10p_5/ vrn_5 io_l10p_5/ vrn_5 io_l10p_5/ vrn_5 ae7 dci 5 n.c. ( ? ) io_l11n_5/ vref_5 io_l11n_5/ vref_5 ab8 vref 5 n.c. ( ? ) io_l11p_5 io_l11p_5 aa8 i/o 5 n.c. ( ? ) io_l12n_5 io_l12n_5 ad8 i/o 5 n.c. ( ? ) io_l12p_5 io_l12p_5 ac8 i/o 5 io_l15n_5 io_l15n_5 io_l15n_5 af8 i/o 5 io_l15p_5 io_l15p_5 io_l15p_5 ae8 i/o 5 io_l16n_5 io_l16n_5 io_l16n_5 aa9 i/o 5 io_l16p_5 io_l16p_5 io_l16p_5 y9 i/o 5 n.c. ( ? ) io_l18n_5 io_l18n_5 ae9 i/o 5 n.c. ( ? ) io_l18p_5 io_l18p_5 ad9 i/o 5 io_l19n_5 io_l19n_5 io_l19n_5 aa10 i/o table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 63 product specification 1-800-255-7778 r 5 io_l19p_5/ vref_5 io_l19p_5/ vref_5 io_l19p_5/ vref_5 y10 vref 5 io_l22n_5 io_l22n_5 io_l22n_5 ac10 i/o 5 io_l22p_5 io_l22p_5 io_l22p_5 ab10 i/o 5 n.c. ( ? ) io_l23n_5 io_l23n_5 af10 i/o 5 n.c. ( ? ) io_l23p_5 io_l23p_5 ae10 i/o 5 io_l24n_5 io_l24n_5 io_l24n_5 y11 i/o 5 io_l24p_5 io_l24p_5 io_l24p_5 w11 i/o 5 io_l25n_5 io_l25n_5 io_l25n_5 ab11 i/o 5 io_l25p_5 io_l25p_5 io_l25p_5 aa11 i/o 5 n.c. ( ? ) io_l26n_5 io_l26n_5 af11 i/o 5 n.c. ( ? ) io_l26p_5 io_l26p_5 ae11 i/o 5 io_l27n_5/ vref_5 io_l27n_5/ vref_5 io_l27n_5/ vref_5 y12 vref 5 io_l27p_5 io_l27p_5 io_l27p_5 w12 i/o 5 io_l28n_5/ d6 io_l28n_5/ d6 io_l28n_5/ d6 ab12 dual 5 io_l28p_5/ d7 io_l28p_5/ d7 io_l28p_5/ d7 aa12 dual 5 io_l29n_5 io_l29n_5 io_l29n_5 af12 i/o 5 io_l29p_5/ vref_5 io_l29p_5/ vref_5 io_l29p_5/ vref_5 ae12 vref 5 io_l30n_5 io_l30n_5 io_l30n_5 y13 i/o 5 io_l30p_5 io_l30p_5 io_l30p_5 w13 i/o 5 io_l31n_5/ d4 io_l31n_5/ d4 io_l31n_5/ d4 ac13 dual 5 io_l31p_5/ d5 io_l31p_5/ d5 io_l31p_5/ d5 ab13 dual 5 io_l32n_5/ gclk3 io_l32n_5/ gclk3 io_l32n_5/ gclk3 ae13 gclk 5 io_l32p_5/ gclk2 io_l32p_5/ gclk2 io_l32p_5/ gclk2 ad13 gclk 5 vcco_5 vcco_5 vcco_5 ad7 vcco 5 vcco_5 vcco_5 vcco_5 ad11 vcco 5 vcco_5 vcco_5 vcco_5 u13 vcco 5 vcco_5 vcco_5 vcco_5 v11 vcco 5 vcco_5 vcco_5 vcco_5 v12 vcco 5 vcco_5 vcco_5 vcco_5 v13 vcco 5 vcco_5 vcco_5 vcco_5 w9 vcco 5 vcco_5 vcco_5 vcco_5 w10 vcco 6 n.c. ( ? ) n.c. ( ? ) io aa5 i/o 6 io_l01n_6/ vrp_6 io_l01n_6/ vrp_6 io_l01n_6/ vrp_6 ad2 dci 6 io_l01p_6/ vrn_6 io_l01p_6/ vrn_6 io_l01p_6/ vrn_6 ad1 dci 6 io_l02n_6 io_l02n_6 io_l02n_6 ab4 i/o 6 io_l02p_6 io_l02p_6 io_l02p_6 ab3 i/o 6 io_l03n_6/ vref_6 io_l03n_6/ vref_6 io_l03n_6/ vref_6 ac2 vref ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 6 io_l03p_6 io_l03p_6 io_l03p_6 ac1 i/o 6 n.c. ( ? ) io_l05n_6 io_l05n_6 ab2 i/o 6 n.c. ( ? ) io_l05p_6 io_l05p_6 ab1 i/o 6 n.c. ( ? ) io_l06n_6 io_l06n_6 y7 i/o 6 n.c. ( ? ) io_l06p_6 io_l06p_6 y6 i/o 6 n.c. ( ? ) io_l07n_6 io_l07n_6 aa4 i/o 6 n.c. ( ? ) io_l07p_6 io_l07p_6 aa3 i/o 6 n.c. ( ? ) io_l08n_6 io_l08n_6 y5 i/o 6 n.c. ( ? ) io_l08p_6 io_l08p_6 y4 i/o 6 n.c. ( ? ) io_l09n_6/ vref_6 io_l09n_6/ vref_6 aa2 vref 6 n.c. ( ? ) io_l09p_6 io_l09p_6 aa1 i/o 6 n.c. ( ? ) io_l10n_6 io_l10n_6 y2 i/o 6 n.c. ( ? ) io_l10p_6 io_l10p_6 y1 i/o 6 io_l14n_6 io_l14n_6 io_l14n_6 w7 i/o 6 io_l14p_6 io_l14p_6 io_l14p_6 w6 i/o 6 io_l16n_6 io_l16n_6 io_l16n_6 v6 i/o 6 io_l16p_6 io_l16p_6 io_l16p_6 w5 i/o 6 io_l17n_6 io_l17n_6 io_l17n_6 w4 i/o 6 io_l17p_6/ vref_6 io_l17p_6/ vref_6 io_l17p_6/ vref_6 w3 vref 6 io_l19n_6 io_l19n_6 io_l19n_6 w2 i/o 6 io_l19p_6 io_l19p_6 io_l19p_6 w1 i/o 6 io_l20n_6 io_l20n_6 io_l20n_6 v7 i/o 6 io_l20p_6 io_l20p_6 io_l20p_6 u7 i/o 6 io_l21n_6 io_l21n_6 io_l21n_6 v5 i/o 6 io_l21p_6 io_l21p_6 io_l21p_6 v4 i/o 6 io_l22n_6 io_l22n_6 io_l22n_6 v3 i/o 6 io_l22p_6 io_l22p_6 io_l22p_6 v2 i/o 6 io_l23n_6 io_l23n_6 io_l23n_6 u6 i/o 6 io_l23p_6 io_l23p_6 io_l23p_6 u5 i/o 6 io_l24n_6/ vref_6 io_l24n_6/ vref_6 io_l24n_6/ vref_6 u4 vref 6 io_l24p_6 io_l24p_6 io_l24p_6 u3 i/o 6 io_l26n_6 io_l26n_6 io_l26n_6 u2 i/o 6 io_l26p_6 io_l26p_6 io_l26p_6 u1 i/o 6 io_l27n_6 io_l27n_6 io_l27n_6 t8 i/o 6 io_l27p_6 io_l27p_6 io_l27p_6 t7 i/o 6 io_l28n_6 io_l28n_6 io_l28n_6 t6 i/o 6 io_l28p_6 io_l28p_6 io_l28p_6 t5 i/o 6 io_l29n_6 io_l29n_6 io_l29n_6 t2 i/o 6 io_l29p_6 io_l29p_6 io_l29p_6 t1 i/o 6 io_l31n_6 io_l31n_6 io_l31n_6 r8 i/o 6 io_l31p_6 io_l31p_6 io_l31p_6 r7 i/o 6 io_l32n_6 io_l32n_6 io_l32n_6 r6 i/o 6 io_l32p_6 io_l32p_6 io_l32p_6 r5 i/o table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions 64 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 6 io_l33n_6 io_l33n_6 io_l33n_6 t4 i/o 6 io_l33p_6 io_l33p_6 io_l33p_6 r3 i/o 6 io_l34n_6/ vref_6 io_l34n_6/ vref_6 io_l34n_6/ vref_6 r2 vref 6 io_l34p_6 io_l34p_6 io_l34p_6 r1 i/o 6 io_l35n_6 io_l35n_6 io_l35n_6 p8 i/o 6 io_l35p_6 io_l35p_6 io_l35p_6 p7 i/o 6 io_l38n_6 io_l38n_6 io_l38n_6 p6 i/o 6 io_l38p_6 io_l38p_6 io_l38p_6 p5 i/o 6 io_l39n_6 io_l39n_6 io_l39n_6 p4 i/o 6 io_l39p_6 io_l39p_6 io_l39p_6 p3 i/o 6 io_l40n_6 io_l40n_6 io_l40n_6 p2 i/o 6 io_l40p_6/ vref_6 io_l40p_6/ vref_6 io_l40p_6/ vref_6 p1 vref 6 vcco_6 vcco_6 vcco_6 p9 vcco 6 vcco_6 vcco_6 vcco_6 p10 vcco 6 vcco_6 vcco_6 vcco_6 r9 vcco 6 vcco_6 vcco_6 vcco_6 t3 vcco 6 vcco_6 vcco_6 vcco_6 t9 vcco 6 vcco_6 vcco_6 vcco_6 u8 vcco 6 vcco_6 vcco_6 vcco_6 v8 vcco 6 vcco_6 vcco_6 vcco_6 y3 vcco 7 io_l01n_7/ vrp_7 io_l01n_7/ vrp_7 io_l01n_7/ vrp_7 f5 dci 7 io_l01p_7/ vrn_7 io_l01p_7/ vrn_7 io_l01p_7/ vrn_7 f6 dci 7 io_l02n_7 io_l02n_7 io_l02n_7 e3 i/o 7 io_l02p_7 io_l02p_7 io_l02p_7 e4 i/o 7 io_l03n_7/ vref_7 io_l03n_7/ vref_7 io_l03n_7/ vref_7 d1 vref 7 io_l03p_7 io_l03p_7 io_l03p_7 d2 i/o 7 n.c. ( ? ) io_l05n_7 io_l05n_7 g6 i/o 7 n.c. ( ? ) io_l05p_7 io_l05p_7 g7 i/o 7 n.c. ( ? ) io_l06n_7 io_l06n_7 e1 i/o 7 n.c. ( ? ) io_l06p_7 io_l06p_7 e2 i/o 7 n.c. ( ? ) io_l07n_7 io_l07n_7 f3 i/o 7 n.c. ( ? ) io_l07p_7 io_l07p_7 f4 i/o 7 n.c. ( ? ) io_l08n_7 io_l08n_7 g4 i/o 7 n.c. ( ? ) io_l08p_7 io_l08p_7 g5 i/o 7 n.c. ( ? ) io_l09n_7 io_l09n_7 f1 i/o 7 n.c. ( ? ) io_l09p_7 io_l09p_7 f2 i/o 7 n.c. ( ? ) io_l10n_7 io_l10n_7 h6 i/o 7 n.c. ( ? ) io_l10p_7/ vref_7 io_l10p_7/ vref_7 h7 vref 7 io_l14n_7 io_l14n_7 io_l14n_7 g1 i/o 7 io_l14p_7 io_l14p_7 io_l14p_7 g2 i/o 7 io_l16n_7 io_l16n_7 io_l16n_7 j6 i/o ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type 7 io_l16p_7/ vref_7 io_l16p_7/ vref_7 io_l16p_7/ vref_7 h5 vref 7 io_l17n_7 io_l17n_7 io_l17n_7 h3 i/o 7 io_l17p_7 io_l17p_7 io_l17p_7 h4 i/o 7 io_l19n_7/ vref_7 io_l19n_7/ vref_7 io_l19n_7/ vref_7 h1 vref 7 io_l19p_7 io_l19p_7 io_l19p_7 h2 i/o 7 io_l20n_7 io_l20n_7 io_l20n_7 k7 i/o 7 io_l20p_7 io_l20p_7 io_l20p_7 j7 i/o 7 io_l21n_7 io_l21n_7 io_l21n_7 j4 i/o 7 io_l21p_7 io_l21p_7 io_l21p_7 j5 i/o 7 io_l22n_7 io_l22n_7 io_l22n_7 j2 i/o 7 io_l22p_7 io_l22p_7 io_l22p_7 j3 i/o 7 io_l23n_7 io_l23n_7 io_l23n_7 k5 i/o 7 io_l23p_7 io_l23p_7 io_l23p_7 k6 i/o 7 io_l24n_7 io_l24n_7 io_l24n_7 k3 i/o 7 io_l24p_7 io_l24p_7 io_l24p_7 k4 i/o 7 io_l26n_7 io_l26n_7 io_l26n_7 k1 i/o 7 io_l26p_7 io_l26p_7 io_l26p_7 k2 i/o 7 io_l27n_7 io_l27n_7 io_l27n_7 l7 i/o 7 io_l27p_7/ vref_7 io_l27p_7/ vref_7 io_l27p_7/ vref_7 l8 vref 7 io_l28n_7 io_l28n_7 io_l28n_7 l5 i/o 7 io_l28p_7 io_l28p_7 io_l28p_7 l6 i/o 7 io_l29n_7 io_l29n_7 io_l29n_7 l1 i/o 7 io_l29p_7 io_l29p_7 io_l29p_7 l2 i/o 7 io_l31n_7 io_l31n_7 io_l31n_7 m7 i/o 7 io_l31p_7 io_l31p_7 io_l31p_7 m8 i/o 7 io_l32n_7 io_l32n_7 io_l32n_7 m6 i/o 7 io_l32p_7 io_l32p_7 io_l32p_7 m5 i/o 7 io_l33n_7 io_l33n_7 io_l33n_7 m3 i/o 7 io_l33p_7 io_l33p_7 io_l33p_7 l4 i/o 7 io_l34n_7 io_l34n_7 io_l34n_7 m1 i/o 7 io_l34p_7 io_l34p_7 io_l34p_7 m2 i/o 7 io_l35n_7 io_l35n_7 io_l35n_7 n7 i/o 7 io_l35p_7 io_l35p_7 io_l35p_7 n8 i/o 7 io_l38n_7 io_l38n_7 io_l38n_7 n5 i/o 7 io_l38p_7 io_l38p_7 io_l38p_7 n6 i/o 7 io_l39n_7 io_l39n_7 io_l39n_7 n3 i/o 7 io_l39p_7 io_l39p_7 io_l39p_7 n4 i/o 7 io_l40n_7/ vref_7 io_l40n_7/ vref_7 io_l40n_7/ vref_7 n1 vref 7 io_l40p_7 io_l40p_7 io_l40p_7 n2 i/o 7 vcco_7 vcco_7 vcco_7 g3 vcco 7 vcco_7 vcco_7 vcco_7 j8 vcco 7 vcco_7 vcco_7 vcco_7 k8 vcco table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 65 product specification 1-800-255-7778 r 7 vcco_7 vcco_7 vcco_7 l3 vcco 7 vcco_7 vcco_7 vcco_7 l9 vcco 7 vcco_7 vcco_7 vcco_7 m9 vcco 7 vcco_7 vcco_7 vcco_7 n9 vcco 7 vcco_7 vcco_7 vcco_7 n10 vcco n/a gnd gnd gnd a1 gnd n/a gnd gnd gnd a26 gnd n/a gnd gnd gnd ac4 gnd n/a gnd gnd gnd ac12 gnd n/a gnd gnd gnd ac15 gnd n/a gnd gnd gnd ac23 gnd n/a gnd gnd gnd ad3 gnd n/a gnd gnd gnd ad24 gnd n/a gnd gnd gnd ae2 gnd n/a gnd gnd gnd ae25 gnd n/a gnd gnd gnd af1 gnd n/a gnd gnd gnd af26 gnd n/a gnd gnd gnd b2 gnd n/a gnd gnd gnd b25 gnd n/a gnd gnd gnd c3 gnd n/a gnd gnd gnd c24 gnd n/a gnd gnd gnd d4 gnd n/a gnd gnd gnd d12 gnd n/a gnd gnd gnd d15 gnd n/a gnd gnd gnd d23 gnd n/a gnd gnd gnd k11 gnd n/a gnd gnd gnd k12 gnd n/a gnd gnd gnd k15 gnd n/a gnd gnd gnd k16 gnd n/a gnd gnd gnd l10 gnd n/a gnd gnd gnd l11 gnd n/a gnd gnd gnd l12 gnd n/a gnd gnd gnd l13 gnd n/a gnd gnd gnd l14 gnd n/a gnd gnd gnd l15 gnd n/a gnd gnd gnd l16 gnd n/a gnd gnd gnd l17 gnd n/a gnd gnd gnd m4 gnd n/a gnd gnd gnd m10 gnd n/a gnd gnd gnd m11 gnd n/a gnd gnd gnd m12 gnd n/a gnd gnd gnd m13 gnd n/a gnd gnd gnd m14 gnd n/a gnd gnd gnd m15 gnd n/a gnd gnd gnd m16 gnd ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type n/a gnd gnd gnd m17 gnd n/a gnd gnd gnd m23 gnd n/a gnd gnd gnd n11 gnd n/a gnd gnd gnd n12 gnd n/a gnd gnd gnd n13 gnd n/a gnd gnd gnd n14 gnd n/a gnd gnd gnd n15 gnd n/a gnd gnd gnd n16 gnd n/a gnd gnd gnd p11 gnd n/a gnd gnd gnd p12 gnd n/a gnd gnd gnd p13 gnd n/a gnd gnd gnd p14 gnd n/a gnd gnd gnd p15 gnd n/a gnd gnd gnd p16 gnd n/a gnd gnd gnd r4 gnd n/a gnd gnd gnd r10 gnd n/a gnd gnd gnd r11 gnd n/a gnd gnd gnd r12 gnd n/a gnd gnd gnd r13 gnd n/a gnd gnd gnd r14 gnd n/a gnd gnd gnd r15 gnd n/a gnd gnd gnd r16 gnd n/a gnd gnd gnd r17 gnd n/a gnd gnd gnd r23 gnd n/a gnd gnd gnd t10 gnd n/a gnd gnd gnd t11 gnd n/a gnd gnd gnd t12 gnd n/a gnd gnd gnd t13 gnd n/a gnd gnd gnd t14 gnd n/a gnd gnd gnd t15 gnd n/a gnd gnd gnd t16 gnd n/a gnd gnd gnd t17 gnd n/a gnd gnd gnd u11 gnd n/a gnd gnd gnd u12 gnd n/a gnd gnd gnd u15 gnd n/a gnd gnd gnd u16 gnd n/a vccaux vccaux vccaux a2 vccaux n/a vccaux vccaux vccaux a9 vccaux n/a vccaux vccaux vccaux a18 vccaux n/a vccaux vccaux vccaux a25 vccaux n/a vccaux vccaux vccaux ae1 vccaux n/a vccaux vccaux vccaux ae26 vccaux n/a vccaux vccaux vccaux af2 vccaux n/a vccaux vccaux vccaux af9 vccaux n/a vccaux vccaux vccaux af18 vccaux table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type
spartan-3 fpga family: pinout descriptions 66 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r user i/os by bank ta b l e 3 1 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks for the xc3s1000 in the fg676 package. similarly, ta b l e 3 2 shows how the available user-i/o pins are distributed between the eight i/o banks for the xc3s1500 in the fg676 package. finally, ta b l e 3 3 shows the same information for the xc3s2000 in the fg676 package. n/a vccaux vccaux vccaux af25 vccaux n/a vccaux vccaux vccaux b1 vccaux n/a vccaux vccaux vccaux b26 vccaux n/a vccaux vccaux vccaux j1 vccaux n/a vccaux vccaux vccaux j26 vccaux n/a vccaux vccaux vccaux v1 vccaux n/a vccaux vccaux vccaux v26 vccaux n/a vccint vccint vccint h8 vccint n/a vccint vccint vccint h19 vccint n/a vccint vccint vccint j9 vccint n/a vccint vccint vccint j10 vccint n/a vccint vccint vccint j17 vccint n/a vccint vccint vccint j18 vccint n/a vccint vccint vccint k9 vccint n/a vccint vccint vccint k10 vccint n/a vccint vccint vccint k17 vccint n/a vccint vccint vccint k18 vccint n/a vccint vccint vccint u9 vccint n/a vccint vccint vccint u10 vccint n/a vccint vccint vccint u17 vccint n/a vccint vccint vccint u18 vccint n/a vccint vccint vccint v9 vccint n/a vccint vccint vccint v10 vccint n/a vccint vccint vccint v17 vccint n/a vccint vccint vccint v18 vccint n/a vccint vccint vccint w8 vccint n/a vccint vccint vccint w19 vccint vcc aux cclk cclk cclk ad26 config ta bl e 3 0 : fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type vcc aux done done done ac24 config vcc aux hswap_en hswap_en hswap_en c2 config vcc aux m0 m0 m0 ae3 config vcc aux m1 m1 m1 ac3 config vcc aux m2 m2 m2 af3 config vcc aux prog_b prog_b prog_b d3 config vcc aux tck tck tck b24 jtag vcc aux tdi tdi tdi c1 jtag vcc aux tdo tdo tdo d24 jtag vcc aux tms tms tms a24 jtag table 30: fg676 package pinout (continued) bank xc3s1000 pin name xc3s1500 pin name xc3s2000 pin name fg676 pin number type ta bl e 3 1 : user i/os per bank for xc3s1000 in fg676 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 49 40 0 2 5 2 1 50 41 0 2 5 2 right 2 48 41 0 2 5 0 3 48 41 0 2 5 0 bottom 4 50 35 6 2 5 2 5 50 35 6 2 5 2 left 6 48 41 0 2 5 0 7 48 41 0 2 5 0
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 67 product specification 1-800-255-7778 r ta bl e 3 2 : user i/os per bank for xc3s1500 in fg676 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 62 52 0 2 6 2 1 61 51 0 2 6 2 right 2 60 52 0 2 6 0 3 60 52 0 2 6 0 bottom 4 63 47 6 2 6 2 5 61 45 6 2 6 2 left 6 60 52 0 2 6 0 7 60 52 0 2 6 0 ta bl e 3 3 : user i/os per bank for xc3s2000 in fg676 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 62 52 0 2 6 2 1 61 51 0 2 6 2 right 2 61 53 0 2 6 0 3 60 52 0 2 6 0 bottom 4 63 47 6 2 6 2 5 61 45 6 2 6 2 left 6 61 53 0 2 6 0 7 60 52 0 2 6 0
spartan-3 fpga family: pinout descriptions 68 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg676 footprint left half of package (top view) xc3s1000 (391 max. user i/o) 315 i/o: unrestricted, general-purpose user i/o 40 vref: user i/o or input voltage reference for bank 98 n.c.: unconnected pins for xc3s1000 ( ? ) xc3s1500 (487 max user i/o) 403 i/o: unrestricted, general-purpose user i/o 48 vref: user i/o or input voltage reference for bank 2 n.c.: unconnected pins for xc3s1500 ( ? ) xc3s2000 (489 max user i/o) 405 i/o: unrestricted, general-purpose user i/o 48 vref: user i/o or input voltage reference for bank 0 n.c.: no unconnected pins all devices 12 dual: configuration pin, then possible user i/o 8 gclk: user i/o or global clock buffer input 16 dci: user i/o or reference resistor input for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 20 vccint: internal core voltage supply (+1.2v) 64 vcco: output voltage supply for bank 16 vccaux: auxiliary voltage supply (+2.5v) 76 gnd: ground figure 14: fg676 package footprint (top view) 2 110 3 4 5 6 7 8 9 111213 bank 0 a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e a f bank 6 bank 7 bank 5 vccaux i/o i/o l05p_0 vref_0 i/o i/o i/o l10p_0 i/o l15p_0 vccaux i/o l23p_0 i/o l26p _0 vref _0 i/o l29p_0 i/o l32p_0 gclk6 vccaux i/o vref_0 i/o l05n_0 i/o l06p_0 i/o l08p_0 i/o l10n_0 i/o l15n_0 i/o l18p_0 i/o l23n_0 i/o l26n_0 i/o l29n_0 i/o l32n_0 gclk7 td i hswap_ en i/o i/o l06n_0 i/o l08n_0 vcco_0 i/o i/o l18n_0 i/o l22p_0 vcco_0 i/o i/o l31p_0 vref_0 i/o l03n_7 vref_7 i/o l03p_7 prog_b i/o l01p_0 vrn_0 i/o l07p_0 i/o l09p_0 i/o l12p_0 i/o l17p_0 i/o l22n_0 i/o l25p_0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o l31n_0 i/o l06n_7 i/o l06p_7 i/o l02n_7 i/o l02p_7 i/o l01n_0 vrp_0 i/o l07n_0 i/o l09n_0 i/o l12n_0 i/o l17n_0 i/o l19p_0 i/o l25n_0 i/o l28p_0 i/o i/o l09n_7 i/o l09p_7 i/o l07n_7 i/o l07p_7 i/o l01n_7 vrp_7 i/o l01p_7 vrn_7 i/o vref_0 i/o l11p_0 i/o l16p_0 i/o l19n_0 i/o l24p_0 i/o l28n_0 i/o l30p_0 i/o l14n_7 i/o l14p_7 vcco_7 i/o l08n_7 i/o l08p_7 i/o l05n_7 i/o l05p_7 i/o l11n_0 i/o l16n_0 i/o vref_0 i/o l24n_0 i/o l27n_0 i/o l30n_0 i/o l19n_7 vref_7 i/o l19p_7 i/o l17n_7 i/o l17p_7 i/o l16p_7 vref_7 i/o l10n_7 i/o l10p _7 vref _7 vccint vcco_0 vcco_0 i/o i/o i/o l27p_0 vccaux i/o l22n_7 i/o l22p_7 i/o l21n_7 i/o l21p_7 i/o l16n_7 i/o l20p_7 vcco_7 vccint vccint vcco_0 vcco_0 vcco_0 i/o l26n_7 i/o l26p_7 i/o l24n_7 i/o l24p_7 i/o l23n_7 i/o l23p_7 i/o l20n_7 vcco_7 vccint vccint vcco_0 i/o l29n_7 i/o l29p_7 vcco_7 i/o l33p_7 i/o l28n_7 i/o l28p_7 i/o l27n_7 i/o l27p_7 vref_7 vcco_7 i/o l34n_7 i/o l34p_7 i/o l33n_7 i/o l32p_7 i/o l32n_7 i/o l31n_7 i/o l31p_7 vcco_7 i/o l40n_7 vref_7 i/o l40p_7 i/o l39n_7 i/o l39p_7 i/o l38n_7 i/o l38p_7 i/o l35n_7 i/o l35p_7 vcco_7 vcco_7 i/o l40p_6 vref_6 i/o l40n_6 i/o l39p_6 i/o l39n_6 i/o l38p_6 i/o l38n_6 i/o l35p_6 i/o l35n_6 vcco_6 vcco_6 i/o l34p_6 i/o l34n_6 vref_6 i/o l33p_6 gnd gnd gnd gnd gnd gnd i/o l32p_6 i/o l32n_6 i/o l31p_6 i/o l31n_6 vcco_6 i/o l29p_6 i/o l29n_6 vcco_6 i/o l33n_6 i/o l28p_6 i/o l28n_6 i/o l27p_6 i/o l27n_6 vcco_6 i/o l26p_6 i/o l26n_6 i/o l24p_6 i/o l24n_6 vref_6 i/o l23p_6 i/o l23n_6 i/o l20p_6 vcco_6 vccint vccint vcco_5 vccaux i/o l22p_6 i/o l22n_6 i/o l21p_6 i/o l21n_6 i/o l16n_6 i/o l20n_6 vcco_6 vccint vccint vcco_5 vcco_5 vcco_5 i/o l19p_6 i/o l19n_6 i/o l17p_6 vref_6 i/o l17n_6 i/o l16p_6 i/o l14p_6 i/o l14n_6 vccint vcco_5 vcco_5 i/o l24p_5 i/o l27p_5 i/o l30p_5 i/o l10p_6 i/o l10n_6 vcco_6 i/o l08p_6 i/o l08n_6 i/o l06p_6 i/o l06n_6 i/o i/o l16p_5 i/o l19p_5 vref_5 i/o l24n_5 i/o l27n_5 vref_5 i/o l30n_5 i/o l09p_6 i/o l09n_6 vref _6 ? i/o l07p_6 i/o l07n_6 i/o ?? i/o l05p_5 i/o i/o l11p_5 i/o l16n_5 i/o l19n_5 i/o l25p_5 i/o l28p_5 d7 i/o i/o l05p_6 i/o l05n_6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ?? ?? ?? ???? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? ? i/o l02p_6 i/o l02n_6 i/o l01p_5 cs_b i/o l05n_5 i/o l09p_5 i/o l11n_5 vref _5 i/o i/o l22p_5 i/o l25n_5 i/o l28n_5 d6 i/o l31p_5 d5 i/o l03p_6 i/o l03n_6 vref_6 m1 i/o l01n_5 rdwr_b i/o l07p_5 i/o l09n_5 i/o l12p_5 i/o i/o l22n_5 i/o gnd gnd gnd gnd gnd i/o l31n_5 d4 i/o l01p_6 vrn_6 i/o l01n_6 vrp_6 i/o l04p_5 i/o l06p_5 i/o l07n_5 vcco_5 i/o l12n_5 i/o l18p_5 i/o vcco_5 i/o i/o l32p_5 gclk2 vccaux m0 i/o l04n_5 i/o l06n_5 i/o l08p_5 i/o l10p_5 vrn_5 i/o l15p_5 i/o l18n_5 i/o l23p_5 i/o l26p_5 i/o l29p_5 vref_5 i/o l32n_5 gclk3 vccaux m2 i/o i/o vref_5 i/o l08n_5 i/o l10n_5 vrp_5 i/o l15n_5 vccaux i/o l23n_5 i/o l26n_5 i/o l29n_5 i/o vref_5 ds099-4_12a_030203
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 69 product specification 1-800-255-7778 r right half of package (top view) 14 15 16 17 18 19 20 21 22 23 24 25 26 bank 1 bank 4 a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e a f bank 2 bank 3 i/o i/o l29n_1 i/o l26n_1 i/o l23n_1 vccaux i/o l15n_1 i/o l10n_1 vref_1 i/o l08n_1 i/o i/o tms vccaux i/o l32n_1 gclk5 i/o l29p_1 i/o l26p_1 i/o l23p_1 i/o l18n_1 i/o l15p_1 i/o l10p_1 i/o l08p_1 i/o l06n_1 vref_1 i/o l04n_1 tck vccaux i/o l32p_1 gclk4 i/o vref_1 vcco_1 i/o vref_1 i/o l18p_1 i/o l12n_1 vcco_1 i/o l07n_1 i/o l06p_1 i/o l04p_1 i/o l01n_2 vrp_2 i/o l01p_2 vrn_2 i/o l31n_1 vref_1 gnd i/o i/o l22n_1 i/o vref_1 i/o l12p_1 i/o l09n_1 i/o l07p_1 i/o l01n_1 vrp_1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd tdo i/o l03n_2 vref_2 i/o l03p_2 i/o l31p_1 i/o l28n_1 i/o l25n_1 i/o l22p_1 i/o i/o l11n_1 i/o l09p_1 i/o l05n_1 i/o l01p_1 vrn_1 i/o l02n_2 i/o l02p_2 i/o l05n_2 i/o l05p_2 i/o i/o l28p_1 i/o l25p_1 i/o l19n_1 i/o l16n_1 i/o l11p_1 i/o i/o l05p_1 i/o ?? i/o l07n_2 i/o l07p_2 i/o l09n_2 vref _2 i/o l09p_2 i/o l30n_1 i/o l27n_1 i/o l24n_1 i/o l19p_1 i/o l16p_1 i/o i/o l06n_2 i/o l06p_2 i/o l08n_2 i/o l08p_2 vcco_2 i/o l10n_2 i/o l10p_2 i/o l30p_1 i/o l27p_1 i/o l24p_1 vcco_1 vcco_1 vccint i/o l14n_2 i/o l14p_2 i/o l16n_2 i/o l17n_2 i/o l17p_2 vref_2 i/o l19n_2 i/o l19p_2 vcco_1 vcco_1 vcco_1 vccint vccint vcco_2 i/o l20n_2 i/o l16p_2 i/o l21n_2 i/o l21p_2 i/o l22n_2 i/o l22p_2 vccaux vcco_1 vccint vccint vcco_2 i/o l20p_2 i/o l23n_2 vref_2 i/o l23p_2 i/o l24n_2 i/o l24p_2 i/o l26n_2 i/o l26p_2 vcco_2 i/o l27n_2 i/o l27p_2 i/o l28n_2 i/o l28p_2 i/o l33n_2 vcco_2 i/o l29n_2 i/o l29p_2 vcco_2 i/o l31n_2 i/o l31p_2 i/o l32n_2 i/o l32p_2 i/o l33p_2 i/o l34n_2 vref_2 i/o l34p_2 vcco_2 vcco_2 i/o l35n_2 i/o l35p_2 i/o l38n_2 i/o l38p_2 i/o l39n_2 i/o l39p_2 i/o l40n_2 i/o l40p_2 vref_2 vcco_3 vcco_3 i/o l35p_3 i/o l35n_3 i/o l38p_3 i/o l38n_3 i/o l39p_3 i/o l39n_3 i/o l40p_3 i/o l40n_3 vref_3 vcco_3 i/o l31p_3 i/o l31n_3 i/o l32p_3 i/o l32n_3 i/o l33n_3 i/o l34p_3 vref_3 i/o l34n_3 vcco_3 i/o l27p_3 i/o l27n_3 i/o l28p_3 i/o l28n_3 i/o l33p_3 vcco_3 i/o l29p_3 i/o l29n_3 vcco_4 vccint vccint vcco_3 i/o l20n_3 i/o l23p_3 vref_3 i/o l23n_3 i/o l24p_3 i/o l24n_3 i/o l26p_3 i/o l26n_3 vcco_4 vcco_4 vcco_4 vccint vccint vcco_3 i/o l20p_3 i/o l16n_3 i/o l21p_3 i/o l21n_3 i/o l22p_3 i/o l22n_3 vccaux i/o l27p_4 d1 i/o i/o vcco_4 vcco_4 vccint i/o l10p_3 i/o l10n_3 i/o l16p_3 i/o l17p_3 vref_3 i/o l17n_3 i/o l19p_3 i/o l19n_3 i/o l30n_4 d2 i/o l27n_4 din d0 i/o l24n_4 i/o vref_4 i/o l16n_4 i/o l11n_4 i/o l05p_3 i/o l05n_3 i/o l08p_3 i/o l08n_3 vcco_3 i/o l14p_3 i/o l14n_3 i/o l30p_4 d3 i/o l28n_4 i/o l24p_4 i/o l19p_4 i/o l16p_4 i/o l11p_4 i/o i/o l01p_3 vrn_3 i/o l01n_3 vrp_3 i/o l07p_3 i/o l07n_3 i/o l09p _3 vref _3 i/o l09n_3 io vref_4 i/o l28p_4 i/o l25n_4 i/o l22p_4 i/o l17n_4 i/o l12n_4 i/o l09n_4 i/o l07n_4 i/o l01n_4 vrp_4 i/o l02p_3 i/o l02n_3 vref_3 i/o l06p_3 i/o l06n_3 i/o l31n_4 init_b i/o l25p_4 i/o l19n_4 i/o l17p_4 i/o l12p_4 i/o l09p_4 i/o l07p_4 i/o l01p_4 vrn_4 done i/o l03p_3 i/o l03n_3 i/o l31p_4 dout bus y i/o vcco_4 i/o l22n_4 vref_4 i/o l18n_4 i/o vcco_4 i/o l08n_4 i/o l06n_4 vref_4 i/o i/o vref_4 cclk i/o l32n_4 gclk1 i/o l29n_4 i/o l26n_4 i/o l23n_4 i/o l18p_4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? i/o l15n_4 i/o l10n_4 i/o l08p_4 i/o l06p_4 i/o l05n_4 i/o l04n_4 vccaux i/o l32p_4 gclk0 i/o l29p_4 i/o l26p _4 vref _4 i/o l23p_4 vccaux i/o l15p_4 i/o l10p_4 i/o i/o i/o l05p_4 i/o l04p_4 vccaux ds099-4_12b_121103
spartan-3 fpga family: pinout descriptions 70 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg900: 900-lead fine -pitch ball grid array the 900-lead fine-pitch ball grid array package, fg900, supports three different spartan-3 devices, including the xc3s2000, the xc3s4000, and the xc3s5000. the foot- prints for the xc3s4000 and xc3s5000 are identical, as shown in ta b l e 3 4 and figure 15 . the xc3s2000, however, has fewer i/o pins which consequently results in 68 uncon- nected pins on the fg900 package, labeled as ?n.c.? in ta bl e 3 4 and figure 15 , these unconnected pins are indi- cated with a black diamond symbol ( ? ). all the package pins appear in ta bl e 3 4 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. if there is a difference between the xc3s2000 pinout and the pinout for the xc3s4000 and xc3s5000, then that dif- ference is highlighted in ta bl e 3 4 . if the table entry is shaded, then there is an unconnected pin on the xc3s2000 that maps to a user-i/o pin on the xc3s4000 and xc3s5000. pinout table ta bl e 3 4 : fg900 package pinout bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 0 io io e15 i/o 0 io io k15 i/o 0 io io d13 i/o 0 io io k13 i/o 0 io io g8 i/o 0 io/vref_0 io/vref_0 f9 vref 0 io/vref_0 io/vref_0 c4 vref 0 io_l01n_0/ vrp_0 io_l01n_0/ vrp_0 b4 dci 0 io_l01p_0/ vrn_0 io_l01p_0/ vrn_0 a4 dci 0 io_l02n_0 io_l02n_0 b5 i/o 0 io_l02p_0 io_l02p_0 a5 i/o 0 io_l03n_0 io_l03n_0 d5 i/o 0 io_l03p_0 io_l03p_0 e6 i/o 0 io_l04n_0 io_l04n_0 c6 i/o 0 io_l04p_0 io_l04p_0 b6 i/o 0 io_l05n_0 io_l05n_0 f6 i/o 0 io_l05p_0/ vref_0 io_l05p_0/ vref_0 f7 vref 0 io_l06n_0 io_l06n_0 d7 i/o 0 io_l06p_0 io_l06p_0 c7 i/o 0 io_l07n_0 io_l07n_0 f8 i/o 0 io_l07p_0 io_l07p_0 e8 i/o 0 io_l08n_0 io_l08n_0 d8 i/o 0 io_l08p_0 io_l08p_0 c8 i/o 0 io_l09n_0 io_l09n_0 b8 i/o 0 io_l09p_0 io_l09p_0 a8 i/o 0 io_l10n_0 io_l10n_0 j9 i/o 0 io_l10p_0 io_l10p_0 h9 i/o 0 io_l11n_0 io_l11n_0 g10 i/o 0 io_l11p_0 io_l11p_0 f10 i/o 0 io_l12n_0 io_l12n_0 c10 i/o 0 io_l12p_0 io_l12p_0 b10 i/o 0 io_l13n_0 io_l13n_0 j10 i/o 0 io_l13p_0 io_l13p_0 k11 i/o 0 io_l14n_0 io_l14n_0 h11 i/o 0 io_l14p_0 io_l14p_0 g11 i/o 0 io_l15n_0 io_l15n_0 f11 i/o 0 io_l15p_0 io_l15p_0 e11 i/o 0 io_l16n_0 io_l16n_0 d11 i/o 0 io_l16p_0 io_l16p_0 c11 i/o 0 io_l17n_0 io_l17n_0 b11 i/o 0 io_l17p_0 io_l17p_0 a11 i/o 0 io_l18n_0 io_l18n_0 k12 i/o 0 io_l18p_0 io_l18p_0 j12 i/o 0 io_l19n_0 io_l19n_0 h12 i/o 0 io_l19p_0 io_l19p_0 g12 i/o 0 io_l20n_0 io_l20n_0 f12 i/o 0 io_l20p_0 io_l20p_0 e12 i/o 0 io_l21n_0 io_l21n_0 d12 i/o 0 io_l21p_0 io_l21p_0 c12 i/o 0 io_l22n_0 io_l22n_0 b12 i/o 0 io_l22p_0 io_l22p_0 a12 i/o 0 io_l23n_0 io_l23n_0 j13 i/o 0 io_l23p_0 io_l23p_0 h13 i/o 0 io_l24n_0 io_l24n_0 f13 i/o 0 io_l24p_0 io_l24p_0 e13 i/o 0 io_l25n_0 io_l25n_0 b13 i/o 0 io_l25p_0 io_l25p_0 a13 i/o 0 io_l26n_0 io_l26n_0 k14 i/o 0 io_l26p_0/ vref_0 io_l26p_0/ vref_0 j14 vref 0 io_l27n_0 io_l27n_0 g14 i/o 0 io_l27p_0 io_l27p_0 f14 i/o 0 io_l28n_0 io_l28n_0 c14 i/o 0 io_l28p_0 io_l28p_0 b14 i/o 0 io_l29n_0 io_l29n_0 j15 i/o table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 71 product specification 1-800-255-7778 r 0 io_l29p_0 io_l29p_0 h15 i/o 0 io_l30n_0 io_l30n_0 g15 i/o 0 io_l30p_0 io_l30p_0 f15 i/o 0 io_l31n_0 io_l31n_0 d15 i/o 0 io_l31p_0/ vref_0 io_l31p_0/ vref_0 c15 vref 0 io_l32n_0/ gclk7 io_l32n_0/ gclk7 b15 gclk 0 io_l32p_0/ gclk6 io_l32p_0/ gclk6 a15 gclk 0 n.c. ( ? ) io_l35n_0 b7 i/o 0 n.c. ( ? ) io_l35p_0 a7 i/o 0 n.c. ( ? ) io_l36n_0 g7 i/o 0 n.c. ( ? ) io_l36p_0 h8 i/o 0 n.c. ( ? ) io_l37n_0 e9 i/o 0 n.c. ( ? ) io_l37p_0 d9 i/o 0 n.c. ( ? ) io_l38n_0 b9 i/o 0 n.c. ( ? ) io_l38p_0 a9 i/o 0 vcco_0 vcco_0 c5 vcco 0 vcco_0 vcco_0 e7 vcco 0 vcco_0 vcco_0 c9 vcco 0 vcco_0 vcco_0 g9 vcco 0 vcco_0 vcco_0 j11 vcco 0 vcco_0 vcco_0 l12 vcco 0 vcco_0 vcco_0 c13 vcco 0 vcco_0 vcco_0 g13 vcco 0 vcco_0 vcco_0 l13 vcco 0 vcco_0 vcco_0 l14 vcco 1 io io e25 i/o 1 io io j21 i/o 1 io io k20 i/o 1 io io f18 i/o 1 io io f16 i/o 1 io io a16 i/o 1 io/vref_1 io/vref_1 j17 vref 1 io_l01n_1/ vrp_1 io_l01n_1/ vrp_1 a27 dci 1 io_l01p_1/ vrn_1 io_l01p_1/ vrn_1 b27 dci 1 io_l02n_1 io_l02n_1 d26 i/o 1 io_l02p_1 io_l02p_1 c27 i/o 1 io_l03n_1 io_l03n_1 a26 i/o 1 io_l03p_1 io_l03p_1 b26 i/o 1 io_l04n_1 io_l04n_1 b25 i/o 1 io_l04p_1 io_l04p_1 c25 i/o 1 io_l05n_1 io_l05n_1 f24 i/o ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 1 io_l05p_1 io_l05p_1 f25 i/o 1 io_l06n_1/ vref_1 io_l06n_1/ vref_1 c24 vref 1 io_l06p_1 io_l06p_1 d24 i/o 1 io_l07n_1 io_l07n_1 a24 i/o 1 io_l07p_1 io_l07p_1 b24 i/o 1 io_l08n_1 io_l08n_1 h23 i/o 1 io_l08p_1 io_l08p_1 g24 i/o 1 io_l09n_1 io_l09n_1 f23 i/o 1 io_l09p_1 io_l09p_1 g23 i/o 1 io_l10n_1/ vref_1 io_l10n_1/ vref_1 c23 vref 1 io_l10p_1 io_l10p_1 d23 i/o 1 io_l11n_1 io_l11n_1 a23 i/o 1 io_l11p_1 io_l11p_1 b23 i/o 1 io_l12n_1 io_l12n_1 h22 i/o 1 io_l12p_1 io_l12p_1 j22 i/o 1 io_l13n_1 io_l13n_1 f22 i/o 1 io_l13p_1 io_l13p_1 e23 i/o 1 io_l14n_1 io_l14n_1 d22 i/o 1 io_l14p_1 io_l14p_1 e22 i/o 1 io_l15n_1 io_l15n_1 a22 i/o 1 io_l15p_1 io_l15p_1 b22 i/o 1 io_l16n_1 io_l16n_1 f21 i/o 1 io_l16p_1 io_l16p_1 g21 i/o 1 io_l17n_1/ vref_1 io_l17n_1/ vref_1 b21 vref 1 io_l17p_1 io_l17p_1 c21 i/o 1 io_l18n_1 io_l18n_1 g20 i/o 1 io_l18p_1 io_l18p_1 h20 i/o 1 io_l19n_1 io_l19n_1 e20 i/o 1 io_l19p_1 io_l19p_1 f20 i/o 1 io_l20n_1 io_l20n_1 c20 i/o 1 io_l20p_1 io_l20p_1 d20 i/o 1 io_l21n_1 io_l21n_1 a20 i/o 1 io_l21p_1 io_l21p_1 b20 i/o 1 io_l22n_1 io_l22n_1 j19 i/o 1 io_l22p_1 io_l22p_1 k19 i/o 1 io_l23n_1 io_l23n_1 g19 i/o 1 io_l23p_1 io_l23p_1 h19 i/o 1 io_l24n_1 io_l24n_1 e19 i/o 1 io_l24p_1 io_l24p_1 f19 i/o 1 io_l25n_1 io_l25n_1 c19 i/o 1 io_l25p_1 io_l25p_1 d19 i/o 1 io_l26n_1 io_l26n_1 a19 i/o table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions 72 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 1 io_l26p_1 io_l26p_1 b19 i/o 1 io_l27n_1 io_l27n_1 f17 i/o 1 io_l27p_1 io_l27p_1 g17 i/o 1 io_l28n_1 io_l28n_1 b17 i/o 1 io_l28p_1 io_l28p_1 c17 i/o 1 io_l29n_1 io_l29n_1 j16 i/o 1 io_l29p_1 io_l29p_1 k16 i/o 1 io_l30n_1 io_l30n_1 g16 i/o 1 io_l30p_1 io_l30p_1 h16 i/o 1 io_l31n_1/ vref_1 io_l31n_1/ vref_1 d16 vref 1 io_l31p_1 io_l31p_1 e16 i/o 1 io_l32n_1/ gclk5 io_l32n_1/ gclk5 b16 gclk 1 io_l32p_1/ gclk4 io_l32p_1/ gclk4 c16 gclk 1 n.c. ( ? ) io_l37n_1 h18 i/o 1 n.c. ( ? ) io_l37p_1 j18 i/o 1 n.c. ( ? ) io_l38n_1 d18 i/o 1 n.c. ( ? ) io_l38p_1 e18 i/o 1 n.c. ( ? ) io_l39n_1 a18 i/o 1 n.c. ( ? ) io_l39p_1 b18 i/o 1 n.c. ( ? ) io_l40n_1 k17 i/o 1 n.c. ( ? ) io_l40p_1 k18 i/o 1 vcco_1 vcco_1 l17 vcco 1 vcco_1 vcco_1 c18 vcco 1 vcco_1 vcco_1 g18 vcco 1 vcco_1 vcco_1 l18 vcco 1 vcco_1 vcco_1 l19 vcco 1 vcco_1 vcco_1 j20 vcco 1 vcco_1 vcco_1 c22 vcco 1 vcco_1 vcco_1 g22 vcco 1 vcco_1 vcco_1 e24 vcco 1 vcco_1 vcco_1 c26 vcco 2 io io j25 i/o 2 io_l01n_2/ vrp_2 io_l01n_2/ vrp_2 c29 dci 2 io_l01p_2/ vrn_2 io_l01p_2/ vrn_2 c30 dci 2 io_l02n_2 io_l02n_2 d27 i/o 2 io_l02p_2 io_l02p_2 d28 i/o 2 io_l03n_2/ vref_2 io_l03n_2/ vref_2 d29 vref 2 io_l03p_2 io_l03p_2 d30 i/o 2 io_l04n_2 io_l04n_2 e29 i/o 2 io_l04p_2 io_l04p_2 e30 i/o ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 2 io_l05n_2 io_l05n_2 f28 i/o 2 io_l05p_2 io_l05p_2 f29 i/o 2 io_l06n_2 io_l06n_2 g27 i/o 2 io_l06p_2 io_l06p_2 g28 i/o 2 io_l07n_2 io_l07n_2 g29 i/o 2 io_l07p_2 io_l07p_2 g30 i/o 2 io_l08n_2 io_l08n_2 g25 i/o 2 io_l08p_2 io_l08p_2 h24 i/o 2 io_l09n_2/ vref_2 io_l09n_2/ vref_2 h25 vref 2 io_l09p_2 io_l09p_2 h26 i/o 2 io_l10n_2 io_l10n_2 h27 i/o 2 io_l10p_2 io_l10p_2 h28 i/o 2 io_l12n_2 io_l12n_2 h29 i/o 2 io_l12p_2 io_l12p_2 h30 i/o 2 io_l13n_2 io_l13n_2 j26 i/o 2 io_l13p_2/ vref_2 io_l13p_2/ vref_2 j27 vref 2 io_l14n_2 io_l14n_2 j29 i/o 2 io_l14p_2 io_l14p_2 j30 i/o 2 io_l15n_2 io_l15n_2 j23 i/o 2 io_l15p_2 io_l15p_2 k22 i/o 2 io_l16n_2 io_l16n_2 k24 i/o 2 io_l16p_2 io_l16p_2 k25 i/o 2 io_l19n_2 io_l19n_2 l25 i/o 2 io_l19p_2 io_l19p_2 l26 i/o 2 io_l20n_2 io_l20n_2 l27 i/o 2 io_l20p_2 io_l20p_2 l28 i/o 2 io_l21n_2 io_l21n_2 l29 i/o 2 io_l21p_2 io_l21p_2 l30 i/o 2 io_l22n_2 io_l22n_2 m22 i/o 2 io_l22p_2 io_l22p_2 m23 i/o 2 io_l23n_2/ vref_2 io_l23n_2/ vref_2 m24 vref 2 io_l23p_2 io_l23p_2 m25 i/o 2 io_l24n_2 io_l24n_2 m27 i/o 2 io_l24p_2 io_l24p_2 m28 i/o 2 io_l26n_2 io_l26n_2 m21 i/o 2 io_l26p_2 io_l26p_2 n21 i/o 2 io_l27n_2 io_l27n_2 n22 i/o 2 io_l27p_2 io_l27p_2 n23 i/o 2 io_l28n_2 io_l28n_2 m26 i/o 2 io_l28p_2 io_l28p_2 n25 i/o 2 io_l29n_2 io_l29n_2 n26 i/o 2 io_l29p_2 io_l29p_2 n27 i/o table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 73 product specification 1-800-255-7778 r 2 io_l31n_2 io_l31n_2 n29 i/o 2 io_l31p_2 io_l31p_2 n30 i/o 2 io_l32n_2 io_l32n_2 p21 i/o 2 io_l32p_2 io_l32p_2 p22 i/o 2 io_l33n_2 io_l33n_2 p24 i/o 2 io_l33p_2 io_l33p_2 p25 i/o 2 io_l34n_2/ vref_2 io_l34n_2/ vref_2 p28 vref 2 io_l34p_2 io_l34p_2 p29 i/o 2 io_l35n_2 io_l35n_2 r21 i/o 2 io_l35p_2 io_l35p_2 r22 i/o 2 io_l37n_2 io_l37n_2 r23 i/o 2 io_l37p_2 io_l37p_2 r24 i/o 2 io_l38n_2 io_l38n_2 r25 i/o 2 io_l38p_2 io_l38p_2 r26 i/o 2 io_l39n_2 io_l39n_2 r27 i/o 2 io_l39p_2 io_l39p_2 r28 i/o 2 io_l40n_2 io_l40n_2 r29 i/o 2 io_l40p_2/ vref_2 io_l40p_2/ vref_2 r30 vref 2 n.c. ( ? ) io_l41n_2 e27 i/o 2 n.c. ( ? ) io_l41p_2 f26 i/o 2 n.c. ( ? ) io_l45n_2 k28 i/o 2 n.c. ( ? ) io_l45p_2 k29 i/o 2 n.c. ( ? ) io_l46n_2 k21 i/o 2 n.c. ( ? ) io_l46p_2 l21 i/o 2 n.c. ( ? ) io_l47n_2 l23 i/o 2 n.c. ( ? ) io_l47p_2 l24 i/o 2 n.c. ( ? ) io_l50n_2 m29 i/o 2 n.c. ( ? ) io_l50p_2 m30 i/o 2 vcco_2 vcco_2 m20 vcco 2 vcco_2 vcco_2 n20 vcco 2 vcco_2 vcco_2 p20 vcco 2 vcco_2 vcco_2 l22 vcco 2 vcco_2 vcco_2 j24 vcco 2 vcco_2 vcco_2 n24 vcco 2 vcco_2 vcco_2 g26 vcco 2 vcco_2 vcco_2 e28 vcco 2 vcco_2 vcco_2 j28 vcco 2 vcco_2 vcco_2 n28 vcco 3 io io ab25 i/o 3 io_l01n_3/ vrp_3 io_l01n_3/ vrp_3 ah30 dci 3 io_l01p_3/ vrn_3 io_l01p_3/ vrn_3 ah29 dci ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 3 io_l02n_3/ vref_3 io_l02n_3/ vref_3 ag28 vref 3 io_l02p_3 io_l02p_3 ag27 i/o 3 io_l03n_3 io_l03n_3 ag30 i/o 3 io_l03p_3 io_l03p_3 ag29 i/o 3 io_l04n_3 io_l04n_3 af30 i/o 3 io_l04p_3 io_l04p_3 af29 i/o 3 io_l05n_3 io_l05n_3 ae26 i/o 3 io_l05p_3 io_l05p_3 af27 i/o 3 io_l06n_3 io_l06n_3 ae29 i/o 3 io_l06p_3 io_l06p_3 ae28 i/o 3 io_l07n_3 io_l07n_3 ad28 i/o 3 io_l07p_3 io_l07p_3 ad27 i/o 3 io_l08n_3 io_l08n_3 ad30 i/o 3 io_l08p_3 io_l08p_3 ad29 i/o 3 io_l09n_3 io_l09n_3 ac24 i/o 3 io_l09p_3/ vref_3 io_l09p_3/ vref_3 ad25 vref 3 io_l10n_3 io_l10n_3 ac26 i/o 3 io_l10p_3 io_l10p_3 ac25 i/o 3 io_l11n_3 io_l11n_3 ac28 i/o 3 io_l11p_3 io_l11p_3 ac27 i/o 3 io_l13n_3/ vref_3 io_l13n_3/ vref_3 ac30 vref 3 io_l13p_3 io_l13p_3 ac29 i/o 3 io_l14n_3 io_l14n_3 ab27 i/o 3 io_l14p_3 io_l14p_3 ab26 i/o 3 io_l15n_3 io_l15n_3 ab30 i/o 3 io_l15p_3 io_l15p_3 ab29 i/o 3 io_l16n_3 io_l16n_3 aa22 i/o 3 io_l16p_3 io_l16p_3 ab23 i/o 3 io_l17n_3 io_l17n_3 aa25 i/o 3 io_l17p_3/ vref_3 io_l17p_3/ vref_3 aa24 vref 3 io_l19n_3 io_l19n_3 aa29 i/o 3 io_l19p_3 io_l19p_3 aa28 i/o 3 io_l20n_3 io_l20n_3 y21 i/o 3 io_l20p_3 io_l20p_3 aa21 i/o 3 io_l21n_3 io_l21n_3 y24 i/o 3 io_l21p_3 io_l21p_3 y23 i/o 3 io_l22n_3 io_l22n_3 y26 i/o 3 io_l22p_3 io_l22p_3 y25 i/o 3 io_l23n_3 io_l23n_3 y28 i/o 3 io_l23p_3/ vref_3 io_l23p_3/ vref_3 y27 vref 3 io_l24n_3 io_l24n_3 y30 i/o table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions 74 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 3 io_l24p_3 io_l24p_3 y29 i/o 3 io_l26n_3 io_l26n_3 w30 i/o 3 io_l26p_3 io_l26p_3 w29 i/o 3 io_l27n_3 io_l27n_3 v21 i/o 3 io_l27p_3 io_l27p_3 w21 i/o 3 io_l28n_3 io_l28n_3 v23 i/o 3 io_l28p_3 io_l28p_3 v22 i/o 3 io_l29n_3 io_l29n_3 v25 i/o 3 io_l29p_3 io_l29p_3 w26 i/o 3 io_l31n_3 io_l31n_3 v30 i/o 3 io_l31p_3 io_l31p_3 v29 i/o 3 io_l32n_3 io_l32n_3 u22 i/o 3 io_l32p_3 io_l32p_3 u21 i/o 3 io_l33n_3 io_l33n_3 u25 i/o 3 io_l33p_3 io_l33p_3 u24 i/o 3 io_l34n_3 io_l34n_3 u29 i/o 3 io_l34p_3/ vref_3 io_l34p_3/ vref_3 u28 vref 3 io_l35n_3 io_l35n_3 t22 i/o 3 io_l35p_3 io_l35p_3 t21 i/o 3 io_l37n_3 io_l37n_3 t24 i/o 3 io_l37p_3 io_l37p_3 t23 i/o 3 io_l38n_3 io_l38n_3 t26 i/o 3 io_l38p_3 io_l38p_3 t25 i/o 3 io_l39n_3 io_l39n_3 t28 i/o 3 io_l39p_3 io_l39p_3 t27 i/o 3 io_l40n_3/ vref_3 io_l40n_3/ vref_3 t30 vref 3 io_l40p_3 io_l40p_3 t29 i/o 3 n.c. ( ? ) io_l46n_3 w23 i/o 3 n.c. ( ? ) io_l46p_3 w22 i/o 3 n.c. ( ? ) io_l47n_3 w25 i/o 3 n.c. ( ? ) io_l47p_3 w24 i/o 3 n.c. ( ? ) io_l48n_3 w28 i/o 3 n.c. ( ? ) io_l48p_3 w27 i/o 3 n.c. ( ? ) io_l50n_3 v27 i/o 3 n.c. ( ? ) io_l50p_3 v26 i/o 3 vcco_3 vcco_3 u20 vcco 3 vcco_3 vcco_3 v20 vcco 3 vcco_3 vcco_3 w20 vcco 3 vcco_3 vcco_3 y22 vcco 3 vcco_3 vcco_3 v24 vcco 3 vcco_3 vcco_3 ab24 vcco 3 vcco_3 vcco_3 ad26 vcco 3 vcco_3 vcco_3 v28 vcco ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 3 vcco_3 vcco_3 ab28 vcco 3 vcco_3 vcco_3 af28 vcco 4 io io aa16 i/o 4 io io ag18 i/o 4 io io aa18 i/o 4 io io ae22 i/o 4 io io ad23 i/o 4 io io ah27 i/o 4 io/vref_4 io/vref_4 af16 vref 4 io/vref_4 io/vref_4 ak28 vref 4 io_l01n_4/ vrp_4 io_l01n_4/ vrp_4 aj27 dci 4 io_l01p_4/ vrn_4 io_l01p_4/ vrn_4 ak27 dci 4 io_l02n_4 io_l02n_4 aj26 i/o 4 io_l02p_4 io_l02p_4 ak26 i/o 4 io_l03n_4 io_l03n_4 ag26 i/o 4 io_l03p_4 io_l03p_4 af25 i/o 4 io_l04n_4 io_l04n_4 ad24 i/o 4 io_l04p_4 io_l04p_4 ac23 i/o 4 io_l05n_4 io_l05n_4 ae23 i/o 4 io_l05p_4 io_l05p_4 af23 i/o 4 io_l06n_4/ vref_4 io_l06n_4/ vref_4 ag23 vref 4 io_l06p_4 io_l06p_4 ah23 i/o 4 io_l07n_4 io_l07n_4 aj23 i/o 4 io_l07p_4 io_l07p_4 ak23 i/o 4 io_l08n_4 io_l08n_4 ab22 i/o 4 io_l08p_4 io_l08p_4 ac22 i/o 4 io_l09n_4 io_l09n_4 af22 i/o 4 io_l09p_4 io_l09p_4 ag22 i/o 4 io_l10n_4 io_l10n_4 aj22 i/o 4 io_l10p_4 io_l10p_4 ak22 i/o 4 io_l11n_4 io_l11n_4 ad21 i/o 4 io_l11p_4 io_l11p_4 ae21 i/o 4 io_l12n_4 io_l12n_4 ah21 i/o 4 io_l12p_4 io_l12p_4 aj21 i/o 4 io_l13n_4 io_l13n_4 ab21 i/o 4 io_l13p_4 io_l13p_4 aa20 i/o 4 io_l14n_4 io_l14n_4 ac20 i/o 4 io_l14p_4 io_l14p_4 ad20 i/o 4 io_l15n_4 io_l15n_4 ae20 i/o 4 io_l15p_4 io_l15p_4 af20 i/o 4 io_l16n_4 io_l16n_4 ag20 i/o 4 io_l16p_4 io_l16p_4 ah20 i/o table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 75 product specification 1-800-255-7778 r 4 io_l17n_4 io_l17n_4 aj20 i/o 4 io_l17p_4 io_l17p_4 ak20 i/o 4 io_l18n_4 io_l18n_4 aa19 i/o 4 io_l18p_4 io_l18p_4 ab19 i/o 4 io_l19n_4 io_l19n_4 ac19 i/o 4 io_l19p_4 io_l19p_4 ad19 i/o 4 io_l20n_4 io_l20n_4 ae19 i/o 4 io_l20p_4 io_l20p_4 af19 i/o 4 io_l21n_4 io_l21n_4 ag19 i/o 4 io_l21p_4 io_l21p_4 ah19 i/o 4 io_l22n_4/ vref_4 io_l22n_4/ vref_4 aj19 vref 4 io_l22p_4 io_l22p_4 ak19 i/o 4 io_l23n_4 io_l23n_4 ab18 i/o 4 io_l23p_4 io_l23p_4 ac18 i/o 4 io_l24n_4 io_l24n_4 ae18 i/o 4 io_l24p_4 io_l24p_4 af18 i/o 4 io_l25n_4 io_l25n_4 aj18 i/o 4 io_l25p_4 io_l25p_4 ak18 i/o 4 io_l26n_4 io_l26n_4 aa17 i/o 4 io_l26p_4/ vref_4 io_l26p_4/ vref_4 ab17 vref 4 io_l27n_4/ din/d0 io_l27n_4/ din/d0 ad17 dual 4 io_l27p_4/ d1 io_l27p_4/ d1 ae17 dual 4 io_l28n_4 io_l28n_4 ah17 i/o 4 io_l28p_4 io_l28p_4 aj17 i/o 4 io_l29n_4 io_l29n_4 ab16 i/o 4 io_l29p_4 io_l29p_4 ac16 i/o 4 io_l30n_4/ d2 io_l30n_4/ d2 ad16 dual 4 io_l30p_4/ d3 io_l30p_4/ d3 ae16 dual 4 io_l31n_4/ init_b io_l31n_4/ init_b ag16 dual 4 io_l31p_4/ dout/busy io_l31p_4/ dout/busy ah16 dual 4 io_l32n_4/ gclk1 io_l32n_4/ gclk1 aj16 gclk 4 io_l32p_4/ gclk0 io_l32p_4/ gclk0 ak16 gclk 4 n.c. ( ? ) io_l33n_4 ah25 i/o 4 n.c. ( ? ) io_l33p_4 aj25 i/o 4 n.c. ( ? ) io_l34n_4 ae25 i/o 4 n.c. ( ? ) io_l34p_4 ae24 i/o 4 n.c. ( ? ) io_l35n_4 ag24 i/o ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 4 n.c. ( ? ) io_l35p_4 ah24 i/o 4 n.c. ( ? ) io_l38n_4 aj24 i/o 4 n.c. ( ? ) io_l38p_4 ak24 i/o 4 vcco_4 vcco_4 y17 vcco 4 vcco_4 vcco_4 y18 vcco 4 vcco_4 vcco_4 ad18 vcco 4 vcco_4 vcco_4 ah18 vcco 4 vcco_4 vcco_4 y19 vcco 4 vcco_4 vcco_4 ab20 vcco 4 vcco_4 vcco_4 ad22 vcco 4 vcco_4 vcco_4 ah22 vcco 4 vcco_4 vcco_4 af24 vcco 4 vcco_4 vcco_4 ah26 vcco 5 io io ae6 i/o 5 io io ab10 i/o 5 io io aa11 i/o 5 io io aa15 i/o 5 io io ae15 i/o 5 io/vref_5 io/vref_5 ah4 vref 5 io/vref_5 io/vref_5 ak15 vref 5 io_l01n_5/ rdwr_b io_l01n_5/ rdwr_b ak4 dual 5 io_l01p_5/ cs_b io_l01p_5/ cs_b aj4 dual 5 io_l02n_5 io_l02n_5 ak5 i/o 5 io_l02p_5 io_l02p_5 aj5 i/o 5 io_l03n_5 io_l03n_5 af6 i/o 5 io_l03p_5 io_l03p_5 ag5 i/o 5 io_l04n_5 io_l04n_5 aj6 i/o 5 io_l04p_5 io_l04p_5 ah6 i/o 5 io_l05n_5 io_l05n_5 ae7 i/o 5 io_l05p_5 io_l05p_5 ad7 i/o 5 io_l06n_5 io_l06n_5 ah7 i/o 5 io_l06p_5 io_l06p_5 ag7 i/o 5 io_l07n_5 io_l07n_5 ak8 i/o 5 io_l07p_5 io_l07p_5 aj8 i/o 5 io_l08n_5 io_l08n_5 ac9 i/o 5 io_l08p_5 io_l08p_5 ab9 i/o 5 io_l09n_5 io_l09n_5 ag9 i/o 5 io_l09p_5 io_l09p_5 af9 i/o 5 io_l10n_5/ vrp_5 io_l10n_5/ vrp_5 ak9 dci 5 io_l10p_5/ vrn_5 io_l10p_5/ vrn_5 aj9 dci 5 io_l11n_5/ vref_5 io_l11n_5/ vref_5 ae10 vref table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions 76 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 5 io_l11p_5 io_l11p_5 ae9 i/o 5 io_l12n_5 io_l12n_5 aj10 i/o 5 io_l12p_5 io_l12p_5 ah10 i/o 5 io_l13n_5 io_l13n_5 ad11 i/o 5 io_l13p_5 io_l13p_5 ad10 i/o 5 io_l14n_5 io_l14n_5 af11 i/o 5 io_l14p_5 io_l14p_5 ae11 i/o 5 io_l15n_5 io_l15n_5 ah11 i/o 5 io_l15p_5 io_l15p_5 ag11 i/o 5 io_l16n_5 io_l16n_5 ak11 i/o 5 io_l16p_5 io_l16p_5 aj11 i/o 5 io_l17n_5 io_l17n_5 ab12 i/o 5 io_l17p_5 io_l17p_5 ac11 i/o 5 io_l18n_5 io_l18n_5 ad12 i/o 5 io_l18p_5 io_l18p_5 ac12 i/o 5 io_l19n_5 io_l19n_5 af12 i/o 5 io_l19p_5/ vref_5 io_l19p_5/ vref_5 ae12 vref 5 io_l20n_5 io_l20n_5 ah12 i/o 5 io_l20p_5 io_l20p_5 ag12 i/o 5 io_l21n_5 io_l21n_5 ak12 i/o 5 io_l21p_5 io_l21p_5 aj12 i/o 5 io_l22n_5 io_l22n_5 aa13 i/o 5 io_l22p_5 io_l22p_5 aa12 i/o 5 io_l23n_5 io_l23n_5 ac13 i/o 5 io_l23p_5 io_l23p_5 ab13 i/o 5 io_l24n_5 io_l24n_5 ag13 i/o 5 io_l24p_5 io_l24p_5 af13 i/o 5 io_l25n_5 io_l25n_5 ak13 i/o 5 io_l25p_5 io_l25p_5 aj13 i/o 5 io_l26n_5 io_l26n_5 ab14 i/o 5 io_l26p_5 io_l26p_5 aa14 i/o 5 io_l27n_5/ vref_5 io_l27n_5/ vref_5 ae14 vref 5 io_l27p_5 io_l27p_5 ae13 i/o 5 io_l28n_5/ d6 io_l28n_5/ d6 aj14 dual 5 io_l28p_5/ d7 io_l28p_5/ d7 ah14 dual 5 io_l29n_5 io_l29n_5 ac15 i/o 5 io_l29p_5/ vref_5 io_l29p_5/ vref_5 ab15 vref 5 io_l30n_5 io_l30n_5 ad15 i/o 5 io_l30p_5 io_l30p_5 ad14 i/o 5 io_l31n_5/ d4 io_l31n_5/ d4 ag15 dual ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 5 io_l31p_5/ d5 io_l31p_5/ d5 af15 dual 5 io_l32n_5/ gclk3 io_l32n_5/ gclk3 aj15 gclk 5 io_l32p_5/ gclk2 io_l32p_5/ gclk2 ah15 gclk 5 n.c. ( ? ) io_l35n_5 ak7 i/o 5 n.c. ( ? ) io_l35p_5 aj7 i/o 5 n.c. ( ? ) io_l36n_5 ad8 i/o 5 n.c. ( ? ) io_l36p_5 ac8 i/o 5 n.c. ( ? ) io_l37n_5 af8 i/o 5 n.c. ( ? ) io_l37p_5 ae8 i/o 5 n.c. ( ? ) io_l38n_5 ah8 i/o 5 n.c. ( ? ) io_l38p_5 ag8 i/o 5 vcco_5 vcco_5 ah5 vcco 5 vcco_5 vcco_5 af7 vcco 5 vcco_5 vcco_5 ad9 vcco 5 vcco_5 vcco_5 ah9 vcco 5 vcco_5 vcco_5 ab11 vcco 5 vcco_5 vcco_5 y12 vcco 5 vcco_5 vcco_5 y13 vcco 5 vcco_5 vcco_5 ad13 vcco 5 vcco_5 vcco_5 ah13 vcco 5 vcco_5 vcco_5 y14 vcco 6 io io ab6 i/o 6 io_l01n_6/ vrp_6 io_l01n_6/ vrp_6 ah2 dci 6 io_l01p_6/ vrn_6 io_l01p_6/ vrn_6 ah1 dci 6 io_l02n_6 io_l02n_6 ag4 i/o 6 io_l02p_6 io_l02p_6 ag3 i/o 6 io_l03n_6/ vref_6 io_l03n_6/ vref_6 ag2 vref 6 io_l03p_6 io_l03p_6 ag1 i/o 6 io_l04n_6 io_l04n_6 af2 i/o 6 io_l04p_6 io_l04p_6 af1 i/o 6 io_l05n_6 io_l05n_6 af4 i/o 6 io_l05p_6 io_l05p_6 ae5 i/o 6 io_l06n_6 io_l06n_6 ae3 i/o 6 io_l06p_6 io_l06p_6 ae2 i/o 6 io_l07n_6 io_l07n_6 ad4 i/o 6 io_l07p_6 io_l07p_6 ad3 i/o 6 io_l08n_6 io_l08n_6 ad2 i/o 6 io_l08p_6 io_l08p_6 ad1 i/o 6 io_l09n_6/ vref_6 io_l09n_6/ vref_6 ad6 vref table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 77 product specification 1-800-255-7778 r 6 io_l09p_6 io_l09p_6 ac7 i/o 6 io_l10n_6 io_l10n_6 ac6 i/o 6 io_l10p_6 io_l10p_6 ac5 i/o 6 io_l11n_6 io_l11n_6 ac4 i/o 6 io_l11p_6 io_l11p_6 ac3 i/o 6 io_l13n_6 io_l13n_6 ac2 i/o 6 io_l13p_6/ vref_6 io_l13p_6/ vref_6 ac1 vref 6 io_l14n_6 io_l14n_6 ab5 i/o 6 io_l14p_6 io_l14p_6 ab4 i/o 6 io_l15n_6 io_l15n_6 ab2 i/o 6 io_l15p_6 io_l15p_6 ab1 i/o 6 io_l16n_6 io_l16n_6 ab8 i/o 6 io_l16p_6 io_l16p_6 aa9 i/o 6 io_l17n_6 io_l17n_6 aa7 i/o 6 io_l17p_6/ vref_6 io_l17p_6/ vref_6 aa6 vref 6 io_l19n_6 io_l19n_6 aa3 i/o 6 io_l19p_6 io_l19p_6 aa2 i/o 6 io_l20n_6 io_l20n_6 aa10 i/o 6 io_l20p_6 io_l20p_6 y10 i/o 6 io_l21n_6 io_l21n_6 y8 i/o 6 io_l21p_6 io_l21p_6 y7 i/o 6 io_l22n_6 io_l22n_6 y6 i/o 6 io_l22p_6 io_l22p_6 y5 i/o 6 io_l24n_6/ vref_6 io_l24n_6/ vref_6 y2 vref 6 io_l24p_6 io_l24p_6 y1 i/o 6 n.c. ( ? ) io_l25n_6 w9 i/o 6 n.c. ( ? ) io_l25p_6 w8 i/o 6 io_l26n_6 io_l26n_6 w7 i/o 6 io_l26p_6 io_l26p_6 w6 i/o 6 io_l27n_6 io_l27n_6 w4 i/o 6 io_l27p_6 io_l27p_6 w3 i/o 6 io_l28n_6 io_l28n_6 w2 i/o 6 io_l28p_6 io_l28p_6 w1 i/o 6 io_l29n_6 io_l29n_6 w10 i/o 6 io_l29p_6 io_l29p_6 v10 i/o 6 n.c. ( ? ) io_l30n_6 v9 i/o 6 n.c. ( ? ) io_l30p_6 v8 i/o 6 io_l31n_6 io_l31n_6 w5 i/o 6 io_l31p_6 io_l31p_6 v6 i/o 6 io_l32n_6 io_l32n_6 v5 i/o 6 io_l32p_6 io_l32p_6 v4 i/o 6 io_l33n_6 io_l33n_6 v2 i/o ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 6 io_l33p_6 io_l33p_6 v1 i/o 6 io_l34n_6/ vref_6 io_l34n_6/ vref_6 u10 vref 6 io_l34p_6 io_l34p_6 u9 i/o 6 io_l35n_6 io_l35n_6 u7 i/o 6 io_l35p_6 io_l35p_6 u6 i/o 6 n.c. ( ? ) io_l36n_6 u3 i/o 6 n.c. ( ? ) io_l36p_6 u2 i/o 6 io_l37n_6 io_l37n_6 t10 i/o 6 io_l37p_6 io_l37p_6 t9 i/o 6 io_l38n_6 io_l38n_6 t6 i/o 6 io_l38p_6 io_l38p_6 t5 i/o 6 io_l39n_6 io_l39n_6 t4 i/o 6 io_l39p_6 io_l39p_6 t3 i/o 6 io_l40n_6 io_l40n_6 t2 i/o 6 io_l40p_6/ vref_6 io_l40p_6/ vref_6 t1 vref 6 n.c. ( ? ) io_l45n_6 y4 i/o 6 n.c. ( ? ) io_l45p_6 y3 i/o 6 n.c. ( ? ) io_l52n_6 t8 i/o 6 n.c. ( ? ) io_l52p_6 t7 i/o 6 vcco_6 vcco_6 v3 vcco 6 vcco_6 vcco_6 ab3 vcco 6 vcco_6 vcco_6 af3 vcco 6 vcco_6 vcco_6 ad5 vcco 6 vcco_6 vcco_6 v7 vcco 6 vcco_6 vcco_6 ab7 vcco 6 vcco_6 vcco_6 y9 vcco 6 vcco_6 vcco_6 u11 vcco 6 vcco_6 vcco_6 v11 vcco 6 vcco_6 vcco_6 w11 vcco 7 io io j6 i/o 7 io_l01n_7/ vrp_7 io_l01n_7/ vrp_7 c1 dci 7 io_l01p_7/ vrn_7 io_l01p_7/ vrn_7 c2 dci 7 io_l02n_7 io_l02n_7 d3 i/o 7 io_l02p_7 io_l02p_7 d4 i/o 7 io_l03n_7/ vref_7 io_l03n_7/ vref_7 d1 vref 7 io_l03p_7 io_l03p_7 d2 i/o 7 io_l04n_7 io_l04n_7 e1 i/o 7 io_l04p_7 io_l04p_7 e2 i/o 7 io_l05n_7 io_l05n_7 f5 i/o 7 io_l05p_7 io_l05p_7 e4 i/o 7 io_l06n_7 io_l06n_7 f2 i/o table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions 78 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 7 io_l06p_7 io_l06p_7 f3 i/o 7 io_l07n_7 io_l07n_7 g3 i/o 7 io_l07p_7 io_l07p_7 g4 i/o 7 io_l08n_7 io_l08n_7 g1 i/o 7 io_l08p_7 io_l08p_7 g2 i/o 7 io_l09n_7 io_l09n_7 h7 i/o 7 io_l09p_7 io_l09p_7 g6 i/o 7 io_l10n_7 io_l10n_7 h5 i/o 7 io_l10p_7/ vref_7 io_l10p_7/ vref_7 h6 vref 7 io_l11n_7 io_l11n_7 h3 i/o 7 io_l11p_7 io_l11p_7 h4 i/o 7 io_l13n_7 io_l13n_7 h1 i/o 7 io_l13p_7 io_l13p_7 h2 i/o 7 io_l14n_7 io_l14n_7 j4 i/o 7 io_l14p_7 io_l14p_7 j5 i/o 7 io_l15n_7 io_l15n_7 j1 i/o 7 io_l15p_7 io_l15p_7 j2 i/o 7 io_l16n_7 io_l16n_7 k9 i/o 7 io_l16p_7/ vref_7 io_l16p_7/ vref_7 j8 vref 7 io_l17n_7 io_l17n_7 k6 i/o 7 io_l17p_7 io_l17p_7 k7 i/o 7 io_l19n_7/ vref_7 io_l19n_7/ vref_7 k2 vref 7 io_l19p_7 io_l19p_7 k3 i/o 7 io_l20n_7 io_l20n_7 l10 i/o 7 io_l20p_7 io_l20p_7 k10 i/o 7 io_l21n_7 io_l21n_7 l7 i/o 7 io_l21p_7 io_l21p_7 l8 i/o 7 io_l22n_7 io_l22n_7 l5 i/o 7 io_l22p_7 io_l22p_7 l6 i/o 7 io_l23n_7 io_l23n_7 l3 i/o 7 io_l23p_7 io_l23p_7 l4 i/o 7 io_l24n_7 io_l24n_7 l1 i/o 7 io_l24p_7 io_l24p_7 l2 i/o 7 n.c. ( ? ) io_l25n_7 m6 i/o 7 n.c. ( ? ) io_l25p_7 m7 i/o 7 io_l26n_7 io_l26n_7 m3 i/o 7 io_l26p_7 io_l26p_7 m4 i/o 7 io_l27n_7 io_l27n_7 m1 i/o 7 io_l27p_7/ vref_7 io_l27p_7/ vref_7 m2 vref 7 io_l28n_7 io_l28n_7 n10 i/o 7 io_l28p_7 io_l28p_7 m10 i/o 7 io_l29n_7 io_l29n_7 n8 i/o ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type 7 io_l29p_7 io_l29p_7 n9 i/o 7 io_l31n_7 io_l31n_7 n1 i/o 7 io_l31p_7 io_l31p_7 n2 i/o 7 io_l32n_7 io_l32n_7 p9 i/o 7 io_l32p_7 io_l32p_7 p10 i/o 7 io_l33n_7 io_l33n_7 p6 i/o 7 io_l33p_7 io_l33p_7 p7 i/o 7 io_l34n_7 io_l34n_7 p2 i/o 7 io_l34p_7 io_l34p_7 p3 i/o 7 io_l35n_7 io_l35n_7 r9 i/o 7 io_l35p_7 io_l35p_7 r10 i/o 7 io_l37n_7 io_l37n_7 r7 i/o 7 io_l37p_7/ vref_7 io_l37p_7/ vref_7 r8 vref 7 io_l38n_7 io_l38n_7 r5 i/o 7 io_l38p_7 io_l38p_7 r6 i/o 7 io_l39n_7 io_l39n_7 r3 i/o 7 io_l39p_7 io_l39p_7 r4 i/o 7 io_l40n_7/ vref_7 io_l40n_7/ vref_7 r1 vref 7 io_l40p_7 io_l40p_7 r2 i/o 7 n.c. ( ? ) io_l46n_7 m8 i/o 7 n.c. ( ? ) io_l46p_7 m9 i/o 7 n.c. ( ? ) io_l49n_7 n6 i/o 7 n.c. ( ? ) io_l49p_7 m5 i/o 7 n.c. ( ? ) io_l50n_7 n4 i/o 7 n.c. ( ? ) io_l50p_7 n5 i/o 7 vcco_7 vcco_7 e3 vcco 7 vcco_7 vcco_7 j3 vcco 7 vcco_7 vcco_7 n3 vcco 7 vcco_7 vcco_7 g5 vcco 7 vcco_7 vcco_7 j7 vcco 7 vcco_7 vcco_7 n7 vcco 7 vcco_7 vcco_7 l9 vcco 7 vcco_7 vcco_7 m11 vcco 7 vcco_7 vcco_7 n11 vcco 7 vcco_7 vcco_7 p11 vcco n/a gnd gnd a1 gnd n/a gnd gnd b1 gnd n/a gnd gnd f1 gnd n/a gnd gnd k1 gnd n/a gnd gnd p1 gnd n/a gnd gnd u1 gnd n/a gnd gnd aa1 gnd n/a gnd gnd ae1 gnd table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 79 product specification 1-800-255-7778 r n/a gnd gnd aj1 gnd n/a gnd gnd ak1 gnd n/a gnd gnd a2 gnd n/a gnd gnd b2 gnd n/a gnd gnd aj2 gnd n/a gnd gnd e5 gnd n/a gnd gnd k5 gnd n/a gnd gnd p5 gnd n/a gnd gnd u5 gnd n/a gnd gnd aa5 gnd n/a gnd gnd af5 gnd n/a gnd gnd a6 gnd n/a gnd gnd ak6 gnd n/a gnd gnd k8 gnd n/a gnd gnd p8 gnd n/a gnd gnd u8 gnd n/a gnd gnd aa8 gnd n/a gnd gnd a10 gnd n/a gnd gnd e10 gnd n/a gnd gnd h10 gnd n/a gnd gnd ac10 gnd n/a gnd gnd af10 gnd n/a gnd gnd ak10 gnd n/a gnd gnd r12 gnd n/a gnd gnd t12 gnd n/a gnd gnd n13 gnd n/a gnd gnd p13 gnd n/a gnd gnd r13 gnd n/a gnd gnd t13 gnd n/a gnd gnd u13 gnd n/a gnd gnd v13 gnd n/a gnd gnd a14 gnd n/a gnd gnd e14 gnd n/a gnd gnd h14 gnd n/a gnd gnd n14 gnd n/a gnd gnd p14 gnd n/a gnd gnd r14 gnd n/a gnd gnd t14 gnd n/a gnd gnd u14 gnd n/a gnd gnd v14 gnd n/a gnd gnd ac14 gnd n/a gnd gnd af14 gnd n/a gnd gnd ak14 gnd n/a gnd gnd m15 gnd n/a gnd gnd n15 gnd ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type n/a gnd gnd p15 gnd n/a gnd gnd r15 gnd n/a gnd gnd t15 gnd n/a gnd gnd u15 gnd n/a gnd gnd v15 gnd n/a gnd gnd w15 gnd n/a gnd gnd m16 gnd n/a gnd gnd n16 gnd n/a gnd gnd p16 gnd n/a gnd gnd r16 gnd n/a gnd gnd t16 gnd n/a gnd gnd u16 gnd n/a gnd gnd v16 gnd n/a gnd gnd w16 gnd n/a gnd gnd a17 gnd n/a gnd gnd e17 gnd n/a gnd gnd h17 gnd n/a gnd gnd n17 gnd n/a gnd gnd p17 gnd n/a gnd gnd r17 gnd n/a gnd gnd t17 gnd n/a gnd gnd u17 gnd n/a gnd gnd v17 gnd n/a gnd gnd ac17 gnd n/a gnd gnd af17 gnd n/a gnd gnd ak17 gnd n/a gnd gnd n18 gnd n/a gnd gnd p18 gnd n/a gnd gnd r18 gnd n/a gnd gnd t18 gnd n/a gnd gnd u18 gnd n/a gnd gnd v18 gnd n/a gnd gnd r19 gnd n/a gnd gnd t19 gnd n/a gnd gnd a21 gnd n/a gnd gnd e21 gnd n/a gnd gnd h21 gnd n/a gnd gnd ac21 gnd n/a gnd gnd af21 gnd n/a gnd gnd ak21 gnd n/a gnd gnd k23 gnd n/a gnd gnd p23 gnd n/a gnd gnd u23 gnd n/a gnd gnd aa23 gnd n/a gnd gnd a25 gnd table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions 80 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r n/a gnd gnd ak25 gnd n/a gnd gnd e26 gnd n/a gnd gnd k26 gnd n/a gnd gnd p26 gnd n/a gnd gnd u26 gnd n/a gnd gnd aa26 gnd n/a gnd gnd af26 gnd n/a gnd gnd a29 gnd n/a gnd gnd b29 gnd n/a gnd gnd aj29 gnd n/a gnd gnd ak29 gnd n/a gnd gnd a30 gnd n/a gnd gnd b30 gnd n/a gnd gnd f30 gnd n/a gnd gnd k30 gnd n/a gnd gnd p30 gnd n/a gnd gnd u30 gnd n/a gnd gnd aa30 gnd n/a gnd gnd ae30 gnd n/a gnd gnd aj30 gnd n/a gnd gnd ak30 gnd n/a gnd gnd ak2 gnd n/a vccaux vccaux f4 vccaux n/a vccaux vccaux k4 vccaux n/a vccaux vccaux p4 vccaux n/a vccaux vccaux u4 vccaux n/a vccaux vccaux aa4 vccaux n/a vccaux vccaux ae4 vccaux n/a vccaux vccaux d6 vccaux n/a vccaux vccaux ag6 vccaux n/a vccaux vccaux d10 vccaux n/a vccaux vccaux ag10 vccaux n/a vccaux vccaux d14 vccaux n/a vccaux vccaux ag14 vccaux n/a vccaux vccaux d17 vccaux n/a vccaux vccaux ag17 vccaux n/a vccaux vccaux d21 vccaux n/a vccaux vccaux ag21 vccaux n/a vccaux vccaux d25 vccaux n/a vccaux vccaux ag25 vccaux n/a vccaux vccaux f27 vccaux n/a vccaux vccaux k27 vccaux n/a vccaux vccaux p27 vccaux n/a vccaux vccaux u27 vccaux n/a vccaux vccaux aa27 vccaux ta bl e 3 4 : fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type n/a vccaux vccaux ae27 vccaux n/a vccint vccint l11 vccint n/a vccint vccint r11 vccint n/a vccint vccint t11 vccint n/a vccint vccint y11 vccint n/a vccint vccint m12 vccint n/a vccint vccint n12 vccint n/a vccint vccint p12 vccint n/a vccint vccint u12 vccint n/a vccint vccint v12 vccint n/a vccint vccint w12 vccint n/a vccint vccint m13 vccint n/a vccint vccint w13 vccint n/a vccint vccint m14 vccint n/a vccint vccint w14 vccint n/a vccint vccint l15 vccint n/a vccint vccint y15 vccint n/a vccint vccint l16 vccint n/a vccint vccint y16 vccint n/a vccint vccint m17 vccint n/a vccint vccint w17 vccint n/a vccint vccint m18 vccint n/a vccint vccint w18 vccint n/a vccint vccint m19 vccint n/a vccint vccint n19 vccint n/a vccint vccint p19 vccint n/a vccint vccint u19 vccint n/a vccint vccint v19 vccint n/a vccint vccint w19 vccint n/a vccint vccint l20 vccint n/a vccint vccint r20 vccint n/a vccint vccint t20 vccint n/a vccint vccint y20 vccint vccaux cclk cclk ah28 config vccaux done done aj28 config vccaux hswap_en hswap_en a3 config vccaux m0 m0 aj3 config vccaux m1 m1 ah3 config vccaux m2 m2 ak3 config vccaux prog_b prog_b b3 config vccaux tck tck b28 jtag vccaux tdi tdi c3 jtag vccaux tdo tdo c28 jtag vccaux tms tms a28 jtag table 34: fg900 package pinout (continued) bank xc3s2000 pin name xc3s4000 xc3s5000 pin name fg900 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 81 product specification 1-800-255-7778 r user i/os by bank ta bl e 3 5 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks for the xc3s2000 in the fg900 package. similarly, ta b l e 3 6 shows how the available user-i/o pins are distributed between the eight i/o banks for the xc3s4000 and xc3s5000 in the fg900 package. ta bl e 3 5 : user i/os per bank for xc3s2000 in fg900 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 71 62 0 2 5 2 1 71 62 0 2 5 2 right 2 69 61 0 2 6 0 3 71 62 0 2 7 0 bottom 4 72 57 6 2 5 2 5 71 55 6 2 6 2 left 6 69 60 0 2 7 0 7 71 62 0 2 7 0 ta bl e 3 6 : user i/os per bank for xc3s4000 and xc3s5000 in fg900 package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 79 70 0 2 5 2 1 79 70 0 2 5 2 right 2 79 71 0 2 6 0 3 79 70 0 2 7 0 bottom 4 80 65 6 2 5 2 5 79 63 6 2 6 2 left 6 79 70 0 2 7 0 7 79 70 0 2 7 0
spartan-3 fpga family: pinout descriptions 82 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg900 footprint left half of package (top view) xc3s2000 (565 max. user i/o) 481 i/o: unrestricted, general-purpose user i/o 48 vref: user i/o or input voltage reference for bank 68 n.c.: unconnected pins for xc3s2000 ( ? ) xc3s4000, xc3s5000 (633 max user i/o) 549 i/o: unrestricted, general-purpose user i/o 48 vref: user i/o or input voltage reference for bank 0 n.c.: no unconnected pins in this package all devices 12 dual: configuration pin, then possible user i/o 8 gclk: user i/o or global clock buffer input 16 dci: user i/o or reference resistor input for bank 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 32 vccint: internal core voltage supply (+1.2v) 80 vcco: output voltage supply for bank 24 vccaux: auxiliary voltage supply (+2.5v) 120 gnd: ground figure 15: fg900 package footprint (top view) hswa p_ en i/o l01p_0 vrn_0 i/o l02p_0 i/o l35p_0 i/o l09p_0 i/o l38p_0 i/o l17p_0 i/o l22p_0 i/o l25p_0 i/o l32p_0 gclk6 gclk7 prog_b i/o l01n_0 vrp_0 i/o l02n_0 i/o l04p_0 i/o l35n_0 i/o l09n_0 i/o l38n_0 i/o l12p_0 i/o l17n_0 i/o l22n_0 i/o l25n_0 i/o l28p_0 i/o l32n_0 i/o l01n_7 vrp_7 i/o l01p_7 v rn_ 7 tdi io vref_0 v cco _0 i/o l04n_0 i/o l06p_0 i/o l08p_0 v cco _0 i/o l12n_0 i/o l16p_0 i/o l21p_0 v cco _0 i/o l28n_0 i/o l31p_0 vref_0 i/o l03n_7 vref_7 i/o l03p_7 i/o l02n_7 i/o l02p_7 i/o l03n_0 i/o l06n_0 i/o l08n_0 i/o l37p_0 i/o l16n_0 i/o l21n_0 i/o i/o l31n_0 i/o l04n_7 i/o l04p_7 v cco _7 i/o l05p_7 i/o l03p_0 v cco _0 i/o l07p_0 i/o l37n_0 i/o l15p_0 i/o l20p_0 i/o l24p_0 i/o i/o l06n_7 i/o l06p_7 i/o l05n_7 i/o l05n_0 i/o l05p_0 vref_0 i/o l07n_0 io vref_0 i/o l11p_0 i/o l15n_0 i/o l20n_0 i/o l24n_0 i/o l27p_0 i/o l30p_0 i/o l08n_7 i/o l08p_7 i/o l07n_7 i/o l07p_7 v cco _7 i/o l09p_7 i/o l36n_0 i/o vcco _0 i/o l11n_0 i/o l14p_0 i/o l19p_0 vcco _0 i/o l27n_0 i/o l30n_0 i/o l13n_7 i/o l13p_7 i/o l11n_7 i/o l11p_7 i/o l10n_7 i/o l10p_7 vref_7 i/o l09n_7 i/o l36p_0 i/o l10p_0 i/o l14n_0 i/o l19n_0 i/o l23p_0 i/o l29p_0 i/o l15n_7 i/o l15p_7 v cco _7 i/o l14n_7 i/o l14p_7 i/o v cco _7 i/o l16p_7 vref_7 i/o l10n_0 i/o l13n_0 v cco _0 i/o l18p_0 i/o l23n_0 i/o l26p_0 vref_0 i/o l29n_0 gnd i/o l19n_7 vref_7 i/o l19p_7 vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux i/o l17n_7 i/o l17p_7 i/o l16n_7 i/o l20p_7 i/o l13p_0 i/o l18n_0 i/o i/o l26n_0 i/o i/o l24n_7 i/o l24p_7 i/o l23n_7 i/o l23p_7 i/o l22n_7 i/o l22p_7 i/o l21n_7 i/o l21p_7 v cco _7 i/o l20n_7 vccint v cco _0 v cco _0 v cco _0 vccint i/o l27n_7 i/o l27p_7 vref_7 i/o l26n_7 i/o l26p_7 i/o l49p_7 i/o l25n_7 i/o l25p_7 i/o l46n_7 i/o l46p_7 i/o l28p_7 v cco _7 vccint vccint vccint gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o l31n_7 i/o l31p_7 v cco _7 i/o l50n_7 i/o l50p_7 i/o l49n_7 v cco _7 i/o l29n_7 i/o l29p_7 i/o l28n_7 v cco _7 vccint gnd i/o l34n_7 i/o l34p_7 gnd i/o l33n_7 i/o l33p_7 gnd i/o l32n_7 i/o l32p_7 v cco _7 vccint i/o l40n_7 vref_7 i/o l40p_7 i/o l39n_7 i/o l39p_7 i/o l38n_7 i/o l38p_7 i/o l37n_7 i/o l37p_7 vref_7 i/o l35n_7 i/o l35p_7 vccint i/o l40p_6 vref_6 i/o l40n_6 i/o l39p_6 i/o l39n_6 i/o l38p_6 i/o l38n_6 i/o l52p_6 i/o l52n_6 i/o l37p_6 i/o l37n_6 vccint gnd i/o l36p_6 i/o l36n_6 gnd i/o l35p_6 i/o l35n_6 gnd i/o l34p_6 i/o l34n_6 vref_6 v cco _6 vccint i/o l33p_6 i/o l33n_6 v cco _6 i/o l32p_6 i/o l32n_6 i/o l31p_6 v cco _6 i/o l30p_6 i/o l30n_6 i/o l29p_6 v cco _6 vccint i/o l28p_6 i/o l28n_6 i/o l27p_6 i/o l27n_6 i/o l31n_6 i/o l26p_6 i/o l26n_6 i/o l25p_6 i/o l25n_6 i/o l29n_6 v cco _6 vccint vccint vccint i/o l24p_6 i/o l24n_6 vref_6 i/o l45p_6 i/o l45n_6 i/o l22p_6 i/o l22n_6 i/o l21p_6 i/o l21n_6 v cco _6 i/o l20p_6 vccint v cco _5 v cco _5 v cco _5 vccint gnd i/o l19p_6 i/o l19n_6 gnd i/o l17p_6 vref_6 i/o l17n_6 gnd i/o l16p_6 i/o l20n_6 i/o i/o l22p_5 i/o l22n_5 i/o l26p_5 i/o i/o l15p_6 i/o l15n_6 v cco _6 i/o l14p_6 i/o l14n_6 i/o v cco _6 i/o l16n_6 i/o l08p_5 i/o v cco _5 i/o l17n_5 i/o l23p_5 i/o l26n_5 i/o l29p_5 vref_5 i/o l13p_6 vref_6 i/o l13n_6 i/o l11p_6 i/o l11n_6 i/o l10p_6 i/o l10n_6 i/o l09p_6 i/o l36p_5 i/o l08n_5 gnd i/o l17p_5 i/o l18p_5 i/o l23n_5 gnd i/o l29n_5 i/o l08p_6 i/o l08n_6 i/o l07p_6 i/o l07n_6 v cco _6 i/o l09n_6 vref_6 i/o l05p_5 i/o l36n_5 v cco _5 i/o l13p_5 i/o l13n_5 i/o l18n_5 v cco _5 i/o l30p_5 i/o l30n_5 gnd i/o l06p_6 i/o l06n_6 vccaux i/o l05p_6 i/o i/o l05n_5 i/o l37p_5 i/o l11p_5 i/o l11n_5 vref_5 i/o l14p_5 i/o l19p_5 vref_5 i/o l27p_5 i/o l27n_5 vref_5 i/o i/o l04p_6 i/o l04n_6 vcco _6 i/o l05n_6 gnd i/o l03n_5 v cco _5 i/o l37n_5 i/o l09p_5 gnd i/o l14n_5 i/o l19n_5 i/o l24p_5 gnd i/o l31p_5 d5 i/o l03p_6 i/o l03n_6 vref_6 i/o l02p_6 i/o l02n_6 i/o l03p_5 i/o l06p_5 i/o l38p_5 i/o l09n_5 i/o l15p_5 i/o l20p_5 i/o l24n_5 v ccaux i/o l31n_5 d4 i/o l01p_6 vrn_6 i/o l01n_6 vrp_6 m1 io vref_5 v cco _5 i/o l04p_5 i/o l06n_5 i/o l38n_5 v cco _5 i/o l12p_5 i/o l15n_5 i/o l20n_5 v cco _5 i/o l28p_5 d7 i/o l32p_5 gnd gnd m0 i/o l01p_5 cs_b i/o l02p_5 i/o l04n_5 i/o l35p_5 i/o l07p_5 i/o l10p_5 vrn_5 i/o l12n_5 i/o l16p_5 i/o l21p_5 i/o l25p_5 i/o l28n_5 d6 i/o l32n_5 gclk3 gclk2 gnd gnd m2 i/o l01n_5 rdwr_b i/o l02n_5 gnd i/o l35n_5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i/o l07n_5 i/o l10n_5 vrp_5 gnd i/o l16n_5 i/o l21n_5 i/o l25n_5 gnd io vref_5 10 11 12 13 14 15 123456789 bank 0 a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e a f a g a h a j a k bank 7 bank 6 bank 5 ds099-4_13a_121103
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 83 product specification 1-800-255-7778 r right half of package (top view) i/o gnd i/o l39n_1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i/o l26n_1 i/o l21n_1 gnd i/o l15n_1 i/o l11n_1 i/o l07n_1 gnd i/o l03n_1 i/o l01n_1 vrp_1 tms gnd gnd i/o l32n_1 i/o l28n_1 i/o l39p_1 i/o l26p_1 i/o l21p_1 i/o l17n_1 vref_1 i/o l15p_1 i/o l11p_1 i/o l07p_1 i/o l04n_1 i/o l03p_1 i/o l01p_1 vrn_1 tck gnd gnd i/o l32p_1 gclk4 gclk5 i/o l28p_1 i/o l25n_1 i/o l20n_1 i/o l17p_1 i/o l10n_1 vref_1 i/o l06n_1 vref_1 i/o l04p_1 i/o l02p_1 tdo i/o l01n_2 vrp_2 i/o l01p_2 vrn_2 i/o l31n_1 vref_1 vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux vccaux i/o l38n_1 i/o l25p_1 i/o l20p_1 i/o l14n_1 i/o l10p_1 i/o l06p_1 i/o l02n_1 i/o l02n_2 i/o l02p_2 i/o l03n_2 vref_2 i/o l03p_2 i/o l31p_1 gnd i/o l38p_1 i/o l24n_1 i/o l19n_1 gnd i/o l14p_1 i/o l13p_1 i/o gnd i/o l41n_2 i/o l04n_2 i/o l04p_2 i/o i/o l27n_1 i/o i/o l24p_1 i/o l19p_1 i/o l16n_1 i/o l13n_1 i/o l09n_1 i/o l05n_1 i/o l05p_1 i/o l41p_2 i/o l05n_2 i/o l05p_2 gnd i/o l30n_1 i/o l27p_1 i/o l23n_1 i/o l18n_1 i/o l16p_1 i/o l09p_1 i/o l08p_1 i/o l08n_2 i/o l06n_2 i/o l06p_2 i/o l07n_2 i/o l07p_2 i/o l30p_1 gnd i/o l37n_1 i/o l23p_1 i/o l18p_1 gnd i/o l12n_1 i/o l08n_1 i/o l08p_2 i/o l09n_2 vref_2 i/o l09p_2 i/o l10n_2 i/o l10p_2 i/o l12n_2 i/o l12p_2 i/o l29n_1 io vref_1 i/o l37p_1 i/o l22n_1 i/o i/o l12p_1 i/o l15n_2 i/o i/o l13n_2 i/o l13p_2 vref_2 i/o l14n_2 i/o l14p_2 i/o l29p_1 i/o l40n_1 i/o l40p_1 i/o l22p_1 i/o i/o l46n_2 i/o l15p_2 gnd i/o l16n_2 i/o l16p_2 gnd i/o l45n_2 i/o l45p_2 gnd vccint vccint i/o l46p_2 i/o l47n_2 i/o l47p_2 i/o l19n_2 i/o l19p_2 i/o l20n_2 i/o l20p_2 i/o l21n_2 i/o l21p_2 gnd vccint vccint vccint i/o l26n_2 i/o l22n_2 i/o l22p_2 i/o l23n_2 vref_2 i/o l23p_2 i/o l28n_2 i/o l24n_2 i/o l24p_2 i/o l50n_2 i/o l50p_2 gnd gnd gnd vccint i/o l26p_2 i/o l27n_2 i/o l27p_2 i/o l28p_2 i/o l29n_2 i/o l29p_2 i/o l31n_2 i/o l31p_2 gnd gnd gnd vccint i/o l32n_2 i/o l32p_2 gnd i/o l33n_2 i/o l33p_2 gnd i/o l34n_2 vref_2 i/o l34p_2 gnd gnd gnd gnd gnd vccint i/o l35n_2 i/o l35p_2 i/o l37n_2 i/o l37p_2 i/o l38n_2 i/o l38p_2 i/o l39n_2 i/o l39p_2 i/o l40n_2 i/o l40p_2 vref_2 gnd gnd gnd gnd vccint i/o l35p_3 i/o l35n_3 i/o l37p_3 i/o l37n_3 i/o l38p_3 i/o l38n_3 i/o l39p_3 i/o l39n_3 i/o l40p_3 i/o l40n_3 vref_3 gnd gnd gnd vccint i/o l32p_3 i/o l32n_3 gnd i/o l33p_3 i/o l33n_3 gnd i/o l34p_3 vref_3 i/o l34n_3 gnd gnd gnd gnd vccint i/o l27n_3 i/o l28p_3 i/o l28n_3 i/o l29n_3 i/o l50p_3 i/o l50n_3 i/o l31p_3 i/o l31n_3 gnd vccint vccint vccint i/o l27p_3 i/o l46p_3 i/o l46n_3 i/o l47p_3 i/o l47n_3 i/o l29p_3 i/o l48p_3 i/o l48n_3 i/o l26p_3 i/o l26n_3 vccint vcco_4 vcco_4 vcco_4 vcco_4 vcco_4 vcco_4 vcco_4 vcco_4 vcco_4 vcco_4 vccint i/o l20n_3 i/o l21p_3 i/o l21n_3 i/o l22p_3 i/o l22n_3 i/o l23p_3 vref_3 i/o l23n_3 i/o l24p_3 i/o l24n_3 i/o i/o l26n_4 i/o i/o l18n_4 i/o l13p_4 i/o l20p_3 i/o l16n_3 gnd i/o l17p_3 vref_3 i/o l17n_3 gnd i/o l19p_3 i/o l19n_3 gnd i/o l29n_4 i/o l26p_4 vref_4 i/o l23n_4 i/o l18p_4 i/o l13n_4 i/o l08n_4 i/o l16p_3 i/o i/o l14p_3 i/o l14n_3 i/o l15p_3 i/o l15n_3 i/o l29p_4 gnd i/o l23p_4 i/o l19n_4 i/o l14n_4 gnd i/o l08p_4 i/o l04p_4 i/o l09n_3 i/o l10p_3 i/o l10n_3 i/o l11p_3 i/o l11n_3 i/o l13p_3 i/o l13n_3 vref_3 i/o l30n_4 d2 i/o l27n_4 din d0 i/o l19p_4 i/o l14p_4 i/o l11n_4 i/o i/o l04n_4 i/o l09p_3 vref_3 i/o l07p_3 i/o l07n_3 i/o l08p_3 i/o l08n_3 i/o l30p_4 d3 i/o l27p_4 d1 i/o l24n_4 i/o l20n_4 i/o l15n_4 i/o l11p_4 i/o i/o l05n_4 i/o l34p_4 i/o l34n_4 i/o l05n_3 i/o l06p_3 i/o l06n_3 gnd i/o vref_4 gnd i/o l24p_4 i/o l20p_4 i/o l15p_4 gnd i/o l09n_4 i/o l05p_4 i/o l03p_4 gnd i/o l05p_3 vcco_3 vcco_3 vcco_3 vcco_3 vcco_3 vcco_3 vcco_3 vcco_3 vcco_2 vcco_2 vcco_2 vcco_2 vcco_2 vcco_2 vcco_1 vcco_1 vcco_1 vcco_1 vcco_1 vcco_1 vcco_1 vcco_1 vcco_1 vcco_1 vcco_2 vcco_2 vcco_2 vcco_2 vcco_3 vcco_3 i/o l04p_3 i/o l04n_3 i/o l31n_4 init_b i/o i/o l21n_4 i/o l16n_4 i/o l09p_4 i/o l06n_4 vref_4 i/o l35n_4 i/o l03n_4 i/o l02p_3 i/o l02n_3 vref_3 i/o l03p_3 i/o l03n_3 i/o l31p_4 dout busy i/o l28n_4 i/o l21p_4 i/o l16p_4 i/o l12n_4 i/o l06p_4 i/o l35p_4 i/o l33n_4 i/o cclk i/o l01p_3 vrn_3 i/o l01n_3 vrp_3 i/o l32n_4 i/o l28p_4 i/o l25n_4 i/o l22n_4 vref_4 i/o l17n_4 i/o l12p_4 i/o l10n_4 i/o l07n_4 i/o l38n_4 i/o l33p_4 i/o l02n_4 i/o l01n_4 vrp_4 done gnd gnd i/o l32p_4 gclk0 gclk1 gnd i/o l25p_4 i/o l22p_4 i/o l17p_4 gnd i/o l10p_4 i/o l07p_4 i/o l38p_4 gnd i/o l02p_4 i/o l01p_4 vrn_ 4 io vref_4 gnd gnd 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 bank 1 a b c d e f g h j k l m n p r t u v w y a a a b a c a d a e a f a g a h a j a k bank 4 bank 2 bank 3 ds099-4_13b_121103
spartan-3 fpga family: pinout descriptions 84 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg1156: 1156-lead fine-pitch ball grid array the 1,156-lead fine-pitch ball grid array package, fg1156, supports two different spartan-3 devices, namely the xc3s4000, and the xc3s5000. the xc3s2000, however, has fewer i/o pins, which consequently results in 73 uncon- nected pins on the fg1156 package, labeled as ?n.c.? in ta bl e 3 7 and figure 16 , these unconnected pins are indi- cated with a black diamond symbol ( ? ). the xc3s5000 has a single unconnected package pin, ball ak31, which is also unconnected for the xc3s4000. all the package pins appear in ta bl e 3 7 and are sorted by bank number, then by pin name. pairs of pins that form a dif- ferential i/o pair appear together in the table. the table also shows the pin number for each pin and the pin type, as defined earlier. if there is a difference between the xc3s2000 and xc3s5000 pinouts, then that difference is highlighted in ta bl e 3 7 . if the table entry is shaded grey, then there is an unconnected pin on the xc3s2000 that maps to a user-i/o pin on the xc3s4000 and xc3s5000. if the table entry is shaded tan, which only occurs on ball l29 in i/o bank 2, then the unconnected pin on xc3s4000 maps to a vref-type pin on the xc3s5000. if the other vref_2 pins all connect to a voltage reference to support a special i/o standard, then also connect the n.c. pin on the xc3s4000 to the same vref_2 voltage. this provides maximum flexi- bility as you could potentially migrate a design from the xc3s4000 to the xc3s5000 fpga without changing the printed circuit board. pinout table ta bl e 3 7 : fg1156 package pinout bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 0 io io b9 i/o 0 io io e17 i/o 0 io io f6 i/o 0 io io f8 i/o 0 io io g12 i/o 0 io io h8 i/o 0 io io h9 i/o 0 io io j11 i/o 0 n.c. ( ? ) io j9 i/o 0 n.c. ( ? ) io k11 i/o 0 io io k13 i/o 0 io io k16 i/o 0 io io k17 i/o 0 io io l13 i/o 0 io io l16 i/o 0 io io l17 i/o 0 io/vref_0 io/vref_0 d5 vref 0 io/vref_0 io/vref_0 e10 vref 0 io/vref_0 io/vref_0 j14 vref 0 io/vref_0 io/vref_0 l15 vref 0 io_l01n_0/ vrp_0 io_l01n_0/ vrp_0 b3 dci 0 io_l01p_0/ vrn_0 io_l01p_0/ vrn_0 a3 dci 0 io_l02n_0 io_l02n_0 b4 i/o 0 io_l02p_0 io_l02p_0 a4 i/o 0 io_l03n_0 io_l03n_0 c5 i/o 0 io_l03p_0 io_l03p_0 b5 i/o 0 io_l04n_0 io_l04n_0 d6 i/o 0 io_l04p_0 io_l04p_0 c6 i/o 0 io_l05n_0 io_l05n_0 b6 i/o 0 io_l05p_0/ vref_0 io_l05p_0/ vref_0 a6 vref 0 io_l06n_0 io_l06n_0 f7 i/o 0 io_l06p_0 io_l06p_0 e7 i/o 0 io_l07n_0 io_l07n_0 g9 i/o 0 io_l07p_0 io_l07p_0 f9 i/o 0 io_l08n_0 io_l08n_0 d9 i/o 0 io_l08p_0 io_l08p_0 c9 i/o 0 io_l09n_0 io_l09n_0 j10 i/o 0 io_l09p_0 io_l09p_0 h10 i/o 0 io_l10n_0 io_l10n_0 g10 i/o 0 io_l10p_0 io_l10p_0 f10 i/o 0 io_l11n_0 io_l11n_0 l12 i/o 0 io_l11p_0 io_l11p_0 k12 i/o 0 io_l12n_0 io_l12n_0 j12 i/o 0 io_l12p_0 io_l12p_0 h12 i/o 0 io_l13n_0 io_l13n_0 f12 i/o 0 io_l13p_0 io_l13p_0 e12 i/o 0 io_l14n_0 io_l14n_0 d12 i/o 0 io_l14p_0 io_l14p_0 c12 i/o 0 io_l15n_0 io_l15n_0 b12 i/o 0 io_l15p_0 io_l15p_0 a12 i/o 0 io_l16n_0 io_l16n_0 h13 i/o 0 io_l16p_0 io_l16p_0 g13 i/o 0 io_l17n_0 io_l17n_0 d13 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 85 product specification 1-800-255-7778 r 0 io_l17p_0 io_l17p_0 c13 i/o 0 io_l18n_0 io_l18n_0 l14 i/o 0 io_l18p_0 io_l18p_0 k14 i/o 0 io_l19n_0 io_l19n_0 h14 i/o 0 io_l19p_0 io_l19p_0 g14 i/o 0 io_l20n_0 io_l20n_0 f14 i/o 0 io_l20p_0 io_l20p_0 e14 i/o 0 io_l21n_0 io_l21n_0 d14 i/o 0 io_l21p_0 io_l21p_0 c14 i/o 0 io_l22n_0 io_l22n_0 b14 i/o 0 io_l22p_0 io_l22p_0 a14 i/o 0 io_l23n_0 io_l23n_0 k15 i/o 0 io_l23p_0 io_l23p_0 j15 i/o 0 io_l24n_0 io_l24n_0 g15 i/o 0 io_l24p_0 io_l24p_0 f15 i/o 0 io_l25n_0 io_l25n_0 d15 i/o 0 io_l25p_0 io_l25p_0 c15 i/o 0 io_l26n_0 io_l26n_0 b15 i/o 0 io_l26p_0/ vref_0 io_l26p_0/ vref_0 a15 vref 0 io_l27n_0 io_l27n_0 g16 i/o 0 io_l27p_0 io_l27p_0 f16 i/o 0 io_l28n_0 io_l28n_0 c16 i/o 0 io_l28p_0 io_l28p_0 b16 i/o 0 io_l29n_0 io_l29n_0 j17 i/o 0 io_l29p_0 io_l29p_0 h17 i/o 0 io_l30n_0 io_l30n_0 g17 i/o 0 io_l30p_0 io_l30p_0 f17 i/o 0 io_l31n_0 io_l31n_0 d17 i/o 0 io_l31p_0/ vref_0 io_l31p_0/ vref_0 c17 vref 0 io_l32n_0/ gclk7 io_l32n_0/ gclk7 b17 gclk 0 io_l32p_0/ gclk6 io_l32p_0/ gclk6 a17 gclk 0 n.c. ( ? ) io_l33n_0 d7 i/o 0 n.c. ( ? ) io_l33p_0 c7 i/o 0 n.c. ( ? ) io_l34n_0 b7 i/o 0 n.c. ( ? ) io_l34p_0 a7 i/o 0 io_l35n_0 io_l35n_0 e8 i/o 0 io_l35p_0 io_l35p_0 d8 i/o 0 io_l36n_0 io_l36n_0 b8 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 0 io_l36p_0 io_l36p_0 a8 i/o 0 io_l37n_0 io_l37n_0 d10 i/o 0 io_l37p_0 io_l37p_0 c10 i/o 0 io_l38n_0 io_l38n_0 b10 i/o 0 io_l38p_0 io_l38p_0 a10 i/o 0 n.c. ( ? ) io_l39n_0 g11 i/o 0 n.c. ( ? ) io_l39p_0 f11 i/o 0 n.c. ( ? ) io_l40n_0 b11 i/o 0 n.c. ( ? ) io_l40p_0 a11 i/o 0 vcco_0 vcco_0 b13 vcco 0 vcco_0 vcco_0 c4 vcco 0 vcco_0 vcco_0 c8 vcco 0 vcco_0 vcco_0 d11 vcco 0 vcco_0 vcco_0 d16 vcco 0 vcco_0 vcco_0 f13 vcco 0 vcco_0 vcco_0 g8 vcco 0 vcco_0 vcco_0 h11 vcco 0 vcco_0 vcco_0 h15 vcco 0 vcco_0 vcco_0 m13 vcco 0 vcco_0 vcco_0 m14 vcco 0 vcco_0 vcco_0 m15 vcco 0 vcco_0 vcco_0 m16 vcco 1io io b26 i/o 1 io io a18 i/o 1 io io c23 i/o 1 io io e21 i/o 1 io io e25 i/o 1 io io f18 i/o 1 io io f27 i/o 1io io f29 i/o 1 io io h23 i/o 1 io io h26 i/o 1 n.c. ( ? ) io j26 i/o 1 io io k19 i/o 1 io io l19 i/o 1 io io l20 i/o 1 io io l21 i/o 1 n.c. ( ? ) io l23 i/o 1 io io l24 i/o 1 io/vref_1 io/vref_1 d30 vref 1 io/vref_1 io/vref_1 k21 vref table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 86 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 1 io/vref_1 io/vref_1 l18 vref 1 io_l01n_1/ vrp_1 io_l01n_1/ vrp_1 a32 dci 1 io_l01p_1/ vrn_1 io_l01p_1/ vrn_1 b32 dci 1 io_l02n_1 io_l02n_1 a31 i/o 1 io_l02p_1 io_l02p_1 b31 i/o 1 io_l03n_1 io_l03n_1 b30 i/o 1 io_l03p_1 io_l03p_1 c30 i/o 1 io_l04n_1 io_l04n_1 c29 i/o 1 io_l04p_1 io_l04p_1 d29 i/o 1 io_l05n_1 io_l05n_1 a29 i/o 1 io_l05p_1 io_l05p_1 b29 i/o 1 io_l06n_1/ vref_1 io_l06n_1/ vref_1 e28 vref 1 io_l06p_1 io_l06p_1 f28 i/o 1 io_l07n_1 io_l07n_1 d27 i/o 1 io_l07p_1 io_l07p_1 e27 i/o 1 io_l08n_1 io_l08n_1 a27 i/o 1 io_l08p_1 io_l08p_1 b27 i/o 1 io_l09n_1 io_l09n_1 f26 i/o 1 io_l09p_1 io_l09p_1 g26 i/o 1 io_l10n_1/ vref_1 io_l10n_1/ vref_1 c26 vref 1 io_l10p_1 io_l10p_1 d26 i/o 1 io_l11n_1 io_l11n_1 h25 i/o 1 io_l11p_1 io_l11p_1 j25 i/o 1 io_l12n_1 io_l12n_1 f25 i/o 1 io_l12p_1 io_l12p_1 g25 i/o 1 io_l13n_1 io_l13n_1 c25 i/o 1 io_l13p_1 io_l13p_1 d25 i/o 1 io_l14n_1 io_l14n_1 a25 i/o 1 io_l14p_1 io_l14p_1 b25 i/o 1 io_l15n_1 io_l15n_1 a24 i/o 1 io_l15p_1 io_l15p_1 b24 i/o 1 io_l16n_1 io_l16n_1 j23 i/o 1 io_l16p_1 io_l16p_1 k23 i/o 1 io_l17n_1/ vref_1 io_l17n_1/ vref_1 f23 vref 1 io_l17p_1 io_l17p_1 g23 i/o 1 io_l18n_1 io_l18n_1 d23 i/o 1 io_l18p_1 io_l18p_1 e23 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 1 io_l19n_1 io_l19n_1 a23 i/o 1 io_l19p_1 io_l19p_1 b23 i/o 1 io_l20n_1 io_l20n_1 k22 i/o 1 io_l20p_1 io_l20p_1 l22 i/o 1 io_l21n_1 io_l21n_1 g22 i/o 1 io_l21p_1 io_l21p_1 h22 i/o 1 io_l22n_1 io_l22n_1 c22 i/o 1 io_l22p_1 io_l22p_1 d22 i/o 1 io_l23n_1 io_l23n_1 h21 i/o 1 io_l23p_1 io_l23p_1 j21 i/o 1 io_l24n_1 io_l24n_1 f21 i/o 1 io_l24p_1 io_l24p_1 g21 i/o 1 io_l25n_1 io_l25n_1 c21 i/o 1 io_l25p_1 io_l25p_1 d21 i/o 1 io_l26n_1 io_l26n_1 a21 i/o 1 io_l26p_1 io_l26p_1 b21 i/o 1 io_l27n_1 io_l27n_1 f19 i/o 1 io_l27p_1 io_l27p_1 g19 i/o 1 io_l28n_1 io_l28n_1 b19 i/o 1 io_l28p_1 io_l28p_1 c19 i/o 1 io_l29n_1 io_l29n_1 j18 i/o 1 io_l29p_1 io_l29p_1 k18 i/o 1 io_l30n_1 io_l30n_1 g18 i/o 1 io_l30p_1 io_l30p_1 h18 i/o 1 io_l31n_1/ vref_1 io_l31n_1/ vref_1 d18 vref 1 io_l31p_1 io_l31p_1 e18 i/o 1 io_l32n_1/ gclk5 io_l32n_1/ gclk5 b18 gclk 1 io_l32p_1/ gclk4 io_l32p_1/ gclk4 c18 gclk 1 n.c. ( ? ) io_l33n_1 c28 i/o 1 n.c. ( ? ) io_l33p_1 d28 i/o 1 n.c. ( ? ) io_l34n_1 a28 i/o 1 n.c. ( ? ) io_l34p_1 b28 i/o 1 n.c. ( ? ) io_l35n_1 j24 i/o 1 n.c. ( ? ) io_l35p_1 k24 i/o 1 n.c. ( ? ) io_l36n_1 f24 i/o 1 n.c. ( ? ) io_l36p_1 g24 i/o 1 io_l37n_1 io_l37n_1 j20 i/o 1 io_l37p_1 io_l37p_1 k20 i/o 1 io_l38n_1 io_l38n_1 f20 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 87 product specification 1-800-255-7778 r 1 io_l38p_1 io_l38p_1 g20 i/o 1 io_l39n_1 io_l39n_1 c20 i/o 1 io_l39p_1 io_l39p_1 d20 i/o 1 io_l40n_1 io_l40n_1 a20 i/o 1 io_l40p_1 io_l40p_1 b20 i/o 1 vcco_1 vcco_1 b22 vcco 1 vcco_1 vcco_1 c27 vcco 1 vcco_1 vcco_1 c31 vcco 1 vcco_1 vcco_1 d19 vcco 1 vcco_1 vcco_1 d24 vcco 1 vcco_1 vcco_1 f22 vcco 1 vcco_1 vcco_1 g27 vcco 1 vcco_1 vcco_1 h20 vcco 1 vcco_1 vcco_1 h24 vcco 1 vcco_1 vcco_1 m19 vcco 1 vcco_1 vcco_1 m20 vcco 1 vcco_1 vcco_1 m21 vcco 1 vcco_1 vcco_1 m22 vcco 2 io io g33 i/o 2 io io g34 i/o 2 io io u25 i/o 2 io io u26 i/o 2 io_l01n_2/ vrp_2 io_l01n_2/ vrp_2 c33 dci 2 io_l01p_2/ vrn_2 io_l01p_2/ vrn_2 c34 dci 2 io_l02n_2 io_l02n_2 d33 i/o 2 io_l02p_2 io_l02p_2 d34 i/o 2 io_l03n_2/ vref_2 io_l03n_2/ vref_2 e32 vref 2 io_l03p_2 io_l03p_2 e33 i/o 2 io_l04n_2 io_l04n_2 f31 i/o 2 io_l04p_2 io_l04p_2 f32 i/o 2 io_l05n_2 io_l05n_2 g29 i/o 2 io_l05p_2 io_l05p_2 g30 i/o 2 io_l06n_2 io_l06n_2 h29 i/o 2 io_l06p_2 io_l06p_2 h30 i/o 2 io_l07n_2 io_l07n_2 h33 i/o 2 io_l07p_2 io_l07p_2 h34 i/o 2 io_l08n_2 io_l08n_2 j28 i/o 2 io_l08p_2 io_l08p_2 j29 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 2 io_l09n_2/ vref_2 io_l09n_2/ vref_2 h31 vref 2 io_l09p_2 io_l09p_2 j31 i/o 2 io_l10n_2 io_l10n_2 j32 i/o 2 io_l10p_2 io_l10p_2 j33 i/o 2 io_l11n_2 io_l11n_2 j27 i/o 2 io_l11p_2 io_l11p_2 k26 i/o 2 io_l12n_2 io_l12n_2 k27 i/o 2 io_l12p_2 io_l12p_2 k28 i/o 2 io_l13n_2 io_l13n_2 k29 i/o 2 io_l13p_2/ vref_2 io_l13p_2/ vref_2 k30 vref 2 io_l14n_2 io_l14n_2 k31 i/o 2 io_l14p_2 io_l14p_2 k32 i/o 2 io_l15n_2 io_l15n_2 k33 i/o 2 io_l15p_2 io_l15p_2 k34 i/o 2 io_l16n_2 io_l16n_2 l25 i/o 2 io_l16p_2 io_l16p_2 l26 i/o 2 n.c. ( ? ) io_l17n_2 l28 i/o 2 n.c. ( ? ) io_l17p_2/ vref_2 l29 vref 2 io_l19n_2 io_l19n_2 m29 i/o 2 io_l19p_2 io_l19p_2 m30 i/o 2 io_l20n_2 io_l20n_2 m31 i/o 2 io_l20p_2 io_l20p_2 m32 i/o 2 io_l21n_2 io_l21n_2 m26 i/o 2 io_l21p_2 io_l21p_2 n25 i/o 2 io_l22n_2 io_l22n_2 n27 i/o 2 io_l22p_2 io_l22p_2 n28 i/o 2 io_l23n_2/ vref_2 io_l23n_2/ vref_2 n31 vref 2 io_l23p_2 io_l23p_2 n32 i/o 2 io_l24n_2 io_l24n_2 n24 i/o 2 io_l24p_2 io_l24p_2 p24 i/o 2 io_l26n_2 io_l26n_2 p29 i/o 2 io_l26p_2 io_l26p_2 p30 i/o 2 io_l27n_2 io_l27n_2 p31 i/o 2 io_l27p_2 io_l27p_2 p32 i/o 2 io_l28n_2 io_l28n_2 p33 i/o 2 io_l28p_2 io_l28p_2 p34 i/o 2 io_l29n_2 io_l29n_2 r24 i/o 2 io_l29p_2 io_l29p_2 r25 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 88 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 2 io_l30n_2 io_l30n_2 r28 i/o 2 io_l30p_2 io_l30p_2 r29 i/o 2 io_l31n_2 io_l31n_2 r31 i/o 2 io_l31p_2 io_l31p_2 r32 i/o 2 io_l32n_2 io_l32n_2 r33 i/o 2 io_l32p_2 io_l32p_2 r34 i/o 2 io_l33n_2 io_l33n_2 r26 i/o 2 io_l33p_2 io_l33p_2 t25 i/o 2 io_l34n_2/ vref_2 io_l34n_2/ vref_2 t28 vref 2 io_l34p_2 io_l34p_2 t29 i/o 2 io_l35n_2 io_l35n_2 t32 i/o 2 io_l35p_2 io_l35p_2 t33 i/o 2 io_l37n_2 io_l37n_2 u27 i/o 2 io_l37p_2 io_l37p_2 u28 i/o 2 io_l38n_2 io_l38n_2 u29 i/o 2 io_l38p_2 io_l38p_2 u30 i/o 2 io_l39n_2 io_l39n_2 u31 i/o 2 io_l39p_2 io_l39p_2 u32 i/o 2 io_l40n_2 io_l40n_2 u33 i/o 2 io_l40p_2/ vref_2 io_l40p_2/ vref_2 u34 vref 2 io_l41n_2 io_l41n_2 f33 i/o 2 io_l41p_2 io_l41p_2 f34 i/o 2 n.c. ( ? ) io_l42n_2 g31 i/o 2 n.c. ( ? ) io_l42p_2 g32 i/o 2 io_l45n_2 io_l45n_2 l33 i/o 2 io_l45p_2 io_l45p_2 l34 i/o 2 io_l46n_2 io_l46n_2 m24 i/o 2 io_l46p_2 io_l46p_2 m25 i/o 2 io_l47n_2 io_l47n_2 m27 i/o 2 io_l47p_2 io_l47p_2 m28 i/o 2 io_l48n_2 io_l48n_2 m33 i/o 2 io_l48p_2 io_l48p_2 m34 i/o 2 n.c. ( ? ) io_l49n_2 p25 i/o 2 n.c. ( ? ) io_l49p_2 p26 i/o 2 io_l50n_2 io_l50n_2 p27 i/o 2 io_l50p_2 io_l50p_2 p28 i/o 2 n.c. ( ? ) io_l51n_2 t24 i/o 2 n.c. ( ? ) io_l51p_2 u24 i/o 2 vcco_2 vcco_2 d32 vcco 2 vcco_2 vcco_2 h28 vcco ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 2 vcco_2 vcco_2 h32 vcco 2 vcco_2 vcco_2 l27 vcco 2 vcco_2 vcco_2 l31 vcco 2 vcco_2 vcco_2 n23 vcco 2 vcco_2 vcco_2 n29 vcco 2 vcco_2 vcco_2 n33 vcco 2 vcco_2 vcco_2 p23 vcco 2 vcco_2 vcco_2 r23 vcco 2 vcco_2 vcco_2 r27 vcco 2 vcco_2 vcco_2 t23 vcco 2 vcco_2 vcco_2 t31 vcco 3io io ah33 i/o 3 io io ah34 i/o 3 io io v25 i/o 3 io io v26 i/o 3 io_l01n_3/ vrp_3 io_l01n_3/ vrp_3 am34 dci 3 io_l01p_3/ vrn_3 io_l01p_3/ vrn_3 am33 dci 3 io_l02n_3/ vref_3 io_l02n_3/ vref_3 al34 vref 3 io_l02p_3 io_l02p_3 al33 i/o 3 io_l03n_3 io_l03n_3 ak33 i/o 3 io_l03p_3 io_l03p_3 ak32 i/o 3 io_l04n_3 io_l04n_3 aj32 i/o 3 io_l04p_3 io_l04p_3 aj31 i/o 3 io_l05n_3 io_l05n_3 aj34 i/o 3 io_l05p_3 io_l05p_3 aj33 i/o 3 io_l06n_3 io_l06n_3 ah30 i/o 3 io_l06p_3 io_l06p_3 ah29 i/o 3 io_l07n_3 io_l07n_3 ag30 i/o 3 io_l07p_3 io_l07p_3 ag29 i/o 3 io_l08n_3 io_l08n_3 ag34 i/o 3 io_l08p_3 io_l08p_3 ag33 i/o 3 io_l09n_3 io_l09n_3 af29 i/o 3 io_l09p_3/ vref_3 io_l09p_3/ vref_3 af28 vref 3 io_l10n_3 io_l10n_3 af31 i/o 3 io_l10p_3 io_l10p_3 ag31 i/o 3 io_l11n_3 io_l11n_3 af33 i/o 3 io_l11p_3 io_l11p_3 af32 i/o 3 io_l12n_3 io_l12n_3 ae26 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 89 product specification 1-800-255-7778 r 3 io_l12p_3 io_l12p_3 af27 i/o 3 io_l13n_3/ vref_3 io_l13n_3/ vref_3 ae28 vref 3 io_l13p_3 io_l13p_3 ae27 i/o 3 io_l14n_3 io_l14n_3 ae30 i/o 3 io_l14p_3 io_l14p_3 ae29 i/o 3 io_l15n_3 io_l15n_3 ae32 i/o 3 io_l15p_3 io_l15p_3 ae31 i/o 3 io_l16n_3 io_l16n_3 ae34 i/o 3 io_l16p_3 io_l16p_3 ae33 i/o 3 io_l17n_3 io_l17n_3 ad26 i/o 3 io_l17p_3/ vref_3 io_l17p_3/ vref_3 ad25 vref 3 io_l19n_3 io_l19n_3 ad34 i/o 3 io_l19p_3 io_l19p_3 ad33 i/o 3 io_l20n_3 io_l20n_3 ac25 i/o 3 io_l20p_3 io_l20p_3 ac24 i/o 3 io_l21n_3 io_l21n_3 ac28 i/o 3 io_l21p_3 io_l21p_3 ac27 i/o 3 io_l22n_3 io_l22n_3 ac30 i/o 3 io_l22p_3 io_l22p_3 ac29 i/o 3 io_l23n_3 io_l23n_3 ac32 i/o 3 io_l23p_3/ vref_3 io_l23p_3/ vref_3 ac31 vref 3 io_l24n_3 io_l24n_3 ab25 i/o 3 io_l24p_3 io_l24p_3 ac26 i/o 3 io_l26n_3 io_l26n_3 aa28 i/o 3 io_l26p_3 io_l26p_3 aa27 i/o 3 io_l27n_3 io_l27n_3 aa30 i/o 3 io_l27p_3 io_l27p_3 aa29 i/o 3 io_l28n_3 io_l28n_3 aa32 i/o 3 io_l28p_3 io_l28p_3 aa31 i/o 3 io_l29n_3 io_l29n_3 aa34 i/o 3 io_l29p_3 io_l29p_3 aa33 i/o 3 io_l30n_3 io_l30n_3 y29 i/o 3 io_l30p_3 io_l30p_3 y28 i/o 3 io_l31n_3 io_l31n_3 y32 i/o 3 io_l31p_3 io_l31p_3 y31 i/o 3 io_l32n_3 io_l32n_3 y34 i/o 3 io_l32p_3 io_l32p_3 y33 i/o 3 io_l33n_3 io_l33n_3 w25 i/o 3 io_l33p_3 io_l33p_3 y26 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 3 io_l34n_3 io_l34n_3 w29 i/o 3 io_l34p_3/ vref_3 io_l34p_3/ vref_3 w28 vref 3 io_l35n_3 io_l35n_3 w33 i/o 3 io_l35p_3 io_l35p_3 w32 i/o 3 io_l37n_3 io_l37n_3 v28 i/o 3 io_l37p_3 io_l37p_3 v27 i/o 3 io_l38n_3 io_l38n_3 v30 i/o 3 io_l38p_3 io_l38p_3 v29 i/o 3 io_l39n_3 io_l39n_3 v32 i/o 3 io_l39p_3 io_l39p_3 v31 i/o 3 io_l40n_3/ vref_3 io_l40n_3/ vref_3 v34 vref 3 io_l40p_3 io_l40p_3 v33 i/o 3 n.c. ( ? ) io_l41n_3 ah32 i/o 3 n.c. ( ? ) io_l41p_3 ah31 i/o 3 n.c. ( ? ) io_l44n_3 ad29 i/o 3 n.c. ( ? ) io_l44p_3 ad28 i/o 3 io_l45n_3 io_l45n_3 ac34 i/o 3 io_l45p_3 io_l45p_3 ac33 i/o 3 io_l46n_3 io_l46n_3 ab28 i/o 3 io_l46p_3 io_l46p_3 ab27 i/o 3 io_l47n_3 io_l47n_3 ab32 i/o 3 io_l47p_3 io_l47p_3 ab31 i/o 3 io_l48n_3 io_l48n_3 aa24 i/o 3 io_l48p_3 io_l48p_3 ab24 i/o 3 n.c. ( ? ) io_l49n_3 aa26 i/o 3 n.c. ( ? ) io_l49p_3 aa25 i/o 3 io_l50n_3 io_l50n_3 y25 i/o 3 io_l50p_3 io_l50p_3 y24 i/o 3 n.c. ( ? ) io_l51n_3 v24 i/o 3 n.c. ( ? ) io_l51p_3 w24 i/o 3 vcco_3 vcco_3 aa23 vcco 3 vcco_3 vcco_3 ab23 vcco 3 vcco_3 vcco_3 ab29 vcco 3 vcco_3 vcco_3 ab33 vcco 3 vcco_3 vcco_3 ad27 vcco 3 vcco_3 vcco_3 ad31 vcco 3 vcco_3 vcco_3 ag28 vcco 3 vcco_3 vcco_3 ag32 vcco 3 vcco_3 vcco_3 al32 vcco 3 vcco_3 vcco_3 w23 vcco table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 90 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 3 vcco_3 vcco_3 w31 vcco 3 vcco_3 vcco_3 y23 vcco 3 vcco_3 vcco_3 y27 vcco 4 io io ad18 i/o 4 io io ad19 i/o 4 io io ad20 i/o 4 io io ad22 i/o 4 io io ae18 i/o 4 io io ae19 i/o 4 io io ae22 i/o 4 n.c. ( ? ) io ae24 i/o 4 io io af24 i/o 4 n.c. ( ? ) io af26 i/o 4 io io ag26 i/o 4 io io ag27 i/o 4 io io aj27 i/o 4 io io aj29 i/o 4 io io ak25 i/o 4 io io an26 i/o 4 io/vref_4 io/vref_4 af21 vref 4 io/vref_4 io/vref_4 ah23 vref 4 io/vref_4 io/vref_4 ak18 vref 4 io/vref_4 io/vref_4 al30 vref 4 io_l01n_4/ vrp_4 io_l01n_4/ vrp_4 an32 dci 4 io_l01p_4/ vrn_4 io_l01p_4/ vrn_4 ap32 dci 4 io_l02n_4 io_l02n_4 an31 i/o 4 io_l02p_4 io_l02p_4 ap31 i/o 4 io_l03n_4 io_l03n_4 am30 i/o 4 io_l03p_4 io_l03p_4 an30 i/o 4 io_l04n_4 io_l04n_4 an27 i/o 4 io_l04p_4 io_l04p_4 ap27 i/o 4 io_l05n_4 io_l05n_4 ah26 i/o 4 io_l05p_4 io_l05p_4 aj26 i/o 4 io_l06n_4/ vref_4 io_l06n_4/ vref_4 al26 vref 4 io_l06p_4 io_l06p_4 am26 i/o 4 io_l07n_4 io_l07n_4 af25 i/o 4 io_l07p_4 io_l07p_4 ag25 i/o 4 io_l08n_4 io_l08n_4 ah25 i/o 4 io_l08p_4 io_l08p_4 aj25 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 4 io_l09n_4 io_l09n_4 al25 i/o 4 io_l09p_4 io_l09p_4 am25 i/o 4 io_l10n_4 io_l10n_4 an25 i/o 4 io_l10p_4 io_l10p_4 ap25 i/o 4 io_l11n_4 io_l11n_4 ad23 i/o 4 io_l11p_4 io_l11p_4 ae23 i/o 4 io_l12n_4 io_l12n_4 af23 i/o 4 io_l12p_4 io_l12p_4 ag23 i/o 4 io_l13n_4 io_l13n_4 aj23 i/o 4 io_l13p_4 io_l13p_4 ak23 i/o 4 io_l14n_4 io_l14n_4 al23 i/o 4 io_l14p_4 io_l14p_4 am23 i/o 4 io_l15n_4 io_l15n_4 an23 i/o 4 io_l15p_4 io_l15p_4 ap23 i/o 4 io_l16n_4 io_l16n_4 ag22 i/o 4 io_l16p_4 io_l16p_4 ah22 i/o 4 io_l17n_4 io_l17n_4 al22 i/o 4 io_l17p_4 io_l17p_4 am22 i/o 4 io_l18n_4 io_l18n_4 ad21 i/o 4 io_l18p_4 io_l18p_4 ae21 i/o 4 io_l19n_4 io_l19n_4 ag21 i/o 4 io_l19p_4 io_l19p_4 ah21 i/o 4 io_l20n_4 io_l20n_4 aj21 i/o 4 io_l20p_4 io_l20p_4 ak21 i/o 4 io_l21n_4 io_l21n_4 al21 i/o 4 io_l21p_4 io_l21p_4 am21 i/o 4 io_l22n_4/ vref_4 io_l22n_4/ vref_4 an21 vref 4 io_l22p_4 io_l22p_4 ap21 i/o 4 io_l23n_4 io_l23n_4 ae20 i/o 4 io_l23p_4 io_l23p_4 af20 i/o 4 io_l24n_4 io_l24n_4 ah20 i/o 4 io_l24p_4 io_l24p_4 aj20 i/o 4 io_l25n_4 io_l25n_4 al20 i/o 4 io_l25p_4 io_l25p_4 am20 i/o 4 io_l26n_4 io_l26n_4 an20 i/o 4 io_l26p_4/ vref_4 io_l26p_4/ vref_4 ap20 vref 4 io_l27n_4/ din/d0 io_l27n_4/ din/d0 ah19 dual 4 io_l27p_4/ d1 io_l27p_4/ d1 aj19 dual table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 91 product specification 1-800-255-7778 r 4 io_l28n_4 io_l28n_4 am19 i/o 4 io_l28p_4 io_l28p_4 an19 i/o 4 io_l29n_4 io_l29n_4 af18 i/o 4 io_l29p_4 io_l29p_4 ag18 i/o 4 io_l30n_4/ d2 io_l30n_4/ d2 ah18 dual 4 io_l30p_4/ d3 io_l30p_4/ d3 aj18 dual 4 io_l31n_4/ init_b io_l31n_4/ init_b al18 dual 4 io_l31p_4/ dout/busy io_l31p_4/ dout/busy am18 dual 4 io_l32n_4/ gclk1 io_l32n_4/ gclk1 an18 gclk 4 io_l32p_4/ gclk0 io_l32p_4/ gclk0 ap18 gclk 4 io_l33n_4 io_l33n_4 al29 i/o 4 io_l33p_4 io_l33p_4 am29 i/o 4 io_l34n_4 io_l34n_4 an29 i/o 4 io_l34p_4 io_l34p_4 ap29 i/o 4 io_l35n_4 io_l35n_4 aj28 i/o 4 io_l35p_4 io_l35p_4 ak28 i/o 4 n.c. ( ? ) io_l36n_4 al28 i/o 4 n.c. ( ? ) io_l36p_4 am28 i/o 4 n.c. ( ? ) io_l37n_4 an28 i/o 4 n.c. ( ? ) io_l37p_4 ap28 i/o 4 io_l38n_4 io_l38n_4 ak27 i/o 4 io_l38p_4 io_l38p_4 al27 i/o 4 n.c. ( ? ) io_l39n_4 ah24 i/o 4 n.c. ( ? ) io_l39p_4 aj24 i/o 4 n.c. ( ? ) io_l40n_4 an24 i/o 4 n.c. ( ? ) io_l40p_4 ap24 i/o 4 vcco_4 vcco_4 ac19 vcco 4 vcco_4 vcco_4 ac20 vcco 4 vcco_4 vcco_4 ac21 vcco 4 vcco_4 vcco_4 ac22 vcco 4 vcco_4 vcco_4 ag20 vcco 4 vcco_4 vcco_4 ag24 vcco 4 vcco_4 vcco_4 ah27 vcco 4 vcco_4 vcco_4 aj22 vcco 4 vcco_4 vcco_4 al19 vcco 4 vcco_4 vcco_4 al24 vcco 4 vcco_4 vcco_4 am27 vcco ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 4 vcco_4 vcco_4 am31 vcco 4 vcco_4 vcco_4 an22 vcco 5io io ad11 i/o 5 n.c. ( ? ) io ad12 i/o 5 io io ad14 i/o 5 io io ad15 i/o 5 io io ad16 i/o 5 io io ad17 i/o 5 io io ae14 i/o 5 io io ae16 i/o 5 n.c. ( ? ) io af9 i/o 5 io io ag9 i/o 5 io io ag12 i/o 5 io io aj6 i/o 5 io io aj17 i/o 5 io io ak10 i/o 5 io io ak14 i/o 5 io io am12 i/o 5 io io an9 i/o 5 io/vref_5 io/vref_5 aj8 vref 5 io/vref_5 io/vref_5 al5 vref 5 io/vref_5 io/vref_5 ap17 vref 5 io_l01n_5/ rdwr_b io_l01n_5/ rdwr_b ap3 dual 5 io_l01p_5/ cs_b io_l01p_5/ cs_b an3 dual 5 io_l02n_5 io_l02n_5 ap4 i/o 5 io_l02p_5 io_l02p_5 an4 i/o 5 io_l03n_5 io_l03n_5 an5 i/o 5 io_l03p_5 io_l03p_5 am5 i/o 5 io_l04n_5 io_l04n_5 am6 i/o 5 io_l04p_5 io_l04p_5 al6 i/o 5 io_l05n_5 io_l05n_5 ap6 i/o 5 io_l05p_5 io_l05p_5 an6 i/o 5 io_l06n_5 io_l06n_5 ak7 i/o 5 io_l06p_5 io_l06p_5 aj7 i/o 5 io_l07n_5 io_l07n_5 ag10 i/o 5 io_l07p_5 io_l07p_5 af10 i/o 5 io_l08n_5 io_l08n_5 aj10 i/o 5 io_l08p_5 io_l08p_5 ah10 i/o 5 io_l09n_5 io_l09n_5 am10 i/o 5 io_l09p_5 io_l09p_5 al10 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 92 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 5 io_l10n_5/ vrp_5 io_l10n_5/ vrp_5 ap10 dci 5 io_l10p_5/ vrn_5 io_l10p_5/ vrn_5 an10 dci 5 io_l11n_5/ vref_5 io_l11n_5/ vref_5 ap11 vref 5 io_l11p_5 io_l11p_5 an11 i/o 5 io_l12n_5 io_l12n_5 af12 i/o 5 io_l12p_5 io_l12p_5 ae12 i/o 5 io_l13n_5 io_l13n_5 aj12 i/o 5 io_l13p_5 io_l13p_5 ah12 i/o 5 io_l14n_5 io_l14n_5 al12 i/o 5 io_l14p_5 io_l14p_5 ak12 i/o 5 io_l15n_5 io_l15n_5 ap12 i/o 5 io_l15p_5 io_l15p_5 an12 i/o 5 io_l16n_5 io_l16n_5 ae13 i/o 5 io_l16p_5 io_l16p_5 ad13 i/o 5 io_l17n_5 io_l17n_5 ah13 i/o 5 io_l17p_5 io_l17p_5 ag13 i/o 5 io_l18n_5 io_l18n_5 am13 i/o 5 io_l18p_5 io_l18p_5 al13 i/o 5 io_l19n_5 io_l19n_5 ag14 i/o 5 io_l19p_5/ vref_5 io_l19p_5/ vref_5 af14 vref 5 io_l20n_5 io_l20n_5 aj14 i/o 5 io_l20p_5 io_l20p_5 ah14 i/o 5 io_l21n_5 io_l21n_5 am14 i/o 5 io_l21p_5 io_l21p_5 al14 i/o 5 io_l22n_5 io_l22n_5 ap14 i/o 5 io_l22p_5 io_l22p_5 an14 i/o 5 io_l23n_5 io_l23n_5 af15 i/o 5 io_l23p_5 io_l23p_5 ae15 i/o 5 io_l24n_5 io_l24n_5 aj15 i/o 5 io_l24p_5 io_l24p_5 ah15 i/o 5 io_l25n_5 io_l25n_5 am15 i/o 5 io_l25p_5 io_l25p_5 al15 i/o 5 io_l26n_5 io_l26n_5 ap15 i/o 5 io_l26p_5 io_l26p_5 an15 i/o 5 io_l27n_5/ vref_5 io_l27n_5/ vref_5 aj16 vref 5 io_l27p_5 io_l27p_5 ah16 i/o 5 io_l28n_5/ d6 io_l28n_5/ d6 an16 dual ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 5 io_l28p_5/ d7 io_l28p_5/ d7 am16 dual 5 io_l29n_5 io_l29n_5 af17 i/o 5 io_l29p_5/ vref_5 io_l29p_5/ vref_5 ae17 vref 5 io_l30n_5 io_l30n_5 ah17 i/o 5 io_l30p_5 io_l30p_5 ag17 i/o 5 io_l31n_5/ d4 io_l31n_5/ d4 al17 dual 5 io_l31p_5/ d5 io_l31p_5/ d5 ak17 dual 5 io_l32n_5/ gclk3 io_l32n_5/ gclk3 an17 gclk 5 io_l32p_5/ gclk2 io_l32p_5/ gclk2 am17 gclk 5 n.c. ( ? ) io_l33n_5 am7 i/o 5 n.c. ( ? ) io_l33p_5 al7 i/o 5 n.c. ( ? ) io_l34n_5 ap7 i/o 5 n.c. ( ? ) io_l34p_5 an7 i/o 5 io_l35n_5 io_l35n_5 al8 i/o 5 io_l35p_5 io_l35p_5 ak8 i/o 5 io_l36n_5 io_l36n_5 ap8 i/o 5 io_l36p_5 io_l36p_5 an8 i/o 5 io_l37n_5 io_l37n_5 aj9 i/o 5 io_l37p_5 io_l37p_5 ah9 i/o 5 io_l38n_5 io_l38n_5 am9 i/o 5 io_l38p_5 io_l38p_5 al9 i/o 5 n.c. ( ? ) io_l39n_5 af11 i/o 5 n.c. ( ? ) io_l39p_5 ae11 i/o 5 n.c. ( ? ) io_l40n_5 aj11 i/o 5 n.c. ( ? ) io_l40p_5 ah11 i/o 5 vcco_5 vcco_5 ac13 vcco 5 vcco_5 vcco_5 ac14 vcco 5 vcco_5 vcco_5 ac15 vcco 5 vcco_5 vcco_5 ac16 vcco 5 vcco_5 vcco_5 ag11 vcco 5 vcco_5 vcco_5 ag15 vcco 5 vcco_5 vcco_5 ah8 vcco 5 vcco_5 vcco_5 aj13 vcco 5 vcco_5 vcco_5 al11 vcco 5 vcco_5 vcco_5 al16 vcco 5 vcco_5 vcco_5 am4 vcco 5 vcco_5 vcco_5 am8 vcco table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 93 product specification 1-800-255-7778 r 5 vcco_5 vcco_5 an13 vcco 6 io io ah1 i/o 6 io io ah2 i/o 6 io io v9 i/o 6 io io v10 i/o 6 io_l01n_6/ vrp_6 io_l01n_6/ vrp_6 am2 dci 6 io_l01p_6/ vrn_6 io_l01p_6/ vrn_6 am1 dci 6 io_l02n_6 io_l02n_6 al2 i/o 6 io_l02p_6 io_l02p_6 al1 i/o 6 io_l03n_6/ vref_6 io_l03n_6/ vref_6 ak3 vref 6 io_l03p_6 io_l03p_6 ak2 i/o 6 io_l04n_6 io_l04n_6 aj4 i/o 6 io_l04p_6 io_l04p_6 aj3 i/o 6 io_l05n_6 io_l05n_6 aj2 i/o 6 io_l05p_6 io_l05p_6 aj1 i/o 6 io_l06n_6 io_l06n_6 ah6 i/o 6 io_l06p_6 io_l06p_6 ah5 i/o 6 io_l07n_6 io_l07n_6 ag6 i/o 6 io_l07p_6 io_l07p_6 ag5 i/o 6 io_l08n_6 io_l08n_6 ag2 i/o 6 io_l08p_6 io_l08p_6 ag1 i/o 6 io_l09n_6/ vref_6 io_l09n_6/ vref_6 af7 vref 6 io_l09p_6 io_l09p_6 af6 i/o 6 io_l10n_6 io_l10n_6 ag4 i/o 6 io_l10p_6 io_l10p_6 af4 i/o 6 io_l11n_6 io_l11n_6 af3 i/o 6 io_l11p_6 io_l11p_6 af2 i/o 6 io_l12n_6 io_l12n_6 af8 i/o 6 io_l12p_6 io_l12p_6 ae9 i/o 6 io_l13n_6 io_l13n_6 ae8 i/o 6 io_l13p_6/ vref_6 io_l13p_6/ vref_6 ae7 vref 6 io_l14n_6 io_l14n_6 ae6 i/o 6 io_l14p_6 io_l14p_6 ae5 i/o 6 io_l15n_6 io_l15n_6 ae4 i/o 6 io_l15p_6 io_l15p_6 ae3 i/o 6 io_l16n_6 io_l16n_6 ae2 i/o 6 io_l16p_6 io_l16p_6 ae1 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 6 io_l17n_6 io_l17n_6 ad10 i/o 6 io_l17p_6/ vref_6 io_l17p_6/ vref_6 ad9 vref 6 io_l19n_6 io_l19n_6 ad2 i/o 6 io_l19p_6 io_l19p_6 ad1 i/o 6 io_l20n_6 io_l20n_6 ac11 i/o 6 io_l20p_6 io_l20p_6 ac10 i/o 6 io_l21n_6 io_l21n_6 ac8 i/o 6 io_l21p_6 io_l21p_6 ac7 i/o 6 io_l22n_6 io_l22n_6 ac6 i/o 6 io_l22p_6 io_l22p_6 ac5 i/o 6 io_l23n_6 io_l23n_6 ac2 i/o 6 io_l23p_6 io_l23p_6 ac1 i/o 6 io_l24n_6/ vref_6 io_l24n_6/ vref_6 ac9 vref 6 io_l24p_6 io_l24p_6 ab10 i/o 6 io_l25n_6 io_l25n_6 ab8 i/o 6 io_l25p_6 io_l25p_6 ab7 i/o 6 io_l26n_6 io_l26n_6 ab4 i/o 6 io_l26p_6 io_l26p_6 ab3 i/o 6 io_l27n_6 io_l27n_6 ab11 i/o 6 io_l27p_6 io_l27p_6 aa11 i/o 6 io_l28n_6 io_l28n_6 aa8 i/o 6 io_l28p_6 io_l28p_6 aa7 i/o 6 io_l29n_6 io_l29n_6 aa6 i/o 6 io_l29p_6 io_l29p_6 aa5 i/o 6 io_l30n_6 io_l30n_6 aa4 i/o 6 io_l30p_6 io_l30p_6 aa3 i/o 6 io_l31n_6 io_l31n_6 aa2 i/o 6 io_l31p_6 io_l31p_6 aa1 i/o 6 io_l32n_6 io_l32n_6 y11 i/o 6 io_l32p_6 io_l32p_6 y10 i/o 6 io_l33n_6 io_l33n_6 y4 i/o 6 io_l33p_6 io_l33p_6 y3 i/o 6 io_l34n_6/ vref_6 io_l34n_6/ vref_6 y2 vref 6 io_l34p_6 io_l34p_6 y1 i/o 6 io_l35n_6 io_l35n_6 y9 i/o 6 io_l35p_6 io_l35p_6 w10 i/o 6 io_l36n_6 io_l36n_6 w7 i/o 6 io_l36p_6 io_l36p_6 w6 i/o 6 io_l37n_6 io_l37n_6 w3 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 94 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r 6 io_l37p_6 io_l37p_6 w2 i/o 6 io_l38n_6 io_l38n_6 v6 i/o 6 io_l38p_6 io_l38p_6 v5 i/o 6 io_l39n_6 io_l39n_6 v4 i/o 6 io_l39p_6 io_l39p_6 v3 i/o 6 io_l40n_6 io_l40n_6 v2 i/o 6 io_l40p_6/ vref_6 io_l40p_6/ vref_6 v1 vref 6 n.c. ( ? ) io_l41n_6 ah4 i/o 6 n.c. ( ? ) io_l41p_6 ah3 i/o 6 n.c. ( ? ) io_l44n_6 ad7 i/o 6 n.c. ( ? ) io_l44p_6 ad6 i/o 6 io_l45n_6 io_l45n_6 ac4 i/o 6 io_l45p_6 io_l45p_6 ac3 i/o 6 n.c. ( ? ) io_l46n_6 aa10 i/o 6 n.c. ( ? ) io_l46p_6 aa9 i/o 6 io_l48n_6 io_l48n_6 y7 i/o 6 io_l48p_6 io_l48p_6 y6 i/o 6 n.c. ( ? ) io_l49n_6 w11 i/o 6 n.c. ( ? ) io_l49p_6 v11 i/o 6 io_l52n_6 io_l52n_6 v8 i/o 6 io_l52p_6 io_l52p_6 v7 i/o 6 vcco_6 vcco_6 aa12 vcco 6 vcco_6 vcco_6 ab12 vcco 6 vcco_6 vcco_6 ab2 vcco 6 vcco_6 vcco_6 ab6 vcco 6 vcco_6 vcco_6 ad4 vcco 6 vcco_6 vcco_6 ad8 vcco 6 vcco_6 vcco_6 ag3 vcco 6 vcco_6 vcco_6 ag7 vcco 6 vcco_6 vcco_6 al3 vcco 6 vcco_6 vcco_6 w12 vcco 6 vcco_6 vcco_6 w4 vcco 6 vcco_6 vcco_6 y12 vcco 6 vcco_6 vcco_6 y8 vcco 7 io io g1 i/o 7 io io g2 i/o 7 io io u10 i/o 7 io io u9 i/o 7 io_l01n_7/ vrp_7 io_l01n_7/ vrp_7 c1 dci ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 7 io_l01p_7/ vrn_7 io_l01p_7/ vrn_7 c2 dci 7 io_l02n_7 io_l02n_7 d1 i/o 7 io_l02p_7 io_l02p_7 d2 i/o 7 io_l03n_7/ vref_7 io_l03n_7/ vref_7 e2 vref 7 io_l03p_7 io_l03p_7 e3 i/o 7 io_l04n_7 io_l04n_7 f3 i/o 7 io_l04p_7 io_l04p_7 f4 i/o 7 io_l05n_7 io_l05n_7 f1 i/o 7 io_l05p_7 io_l05p_7 f2 i/o 7 io_l06n_7 io_l06n_7 g5 i/o 7 io_l06p_7 io_l06p_7 g6 i/o 7 io_l07n_7 io_l07n_7 h5 i/o 7 io_l07p_7 io_l07p_7 h6 i/o 7 io_l08n_7 io_l08n_7 h1 i/o 7 io_l08p_7 io_l08p_7 h2 i/o 7 io_l09n_7 io_l09n_7 j6 i/o 7 io_l09p_7 io_l09p_7 j7 i/o 7 io_l10n_7 io_l10n_7 j4 i/o 7 io_l10p_7/ vref_7 io_l10p_7/ vref_7 h4 vref 7 io_l11n_7 io_l11n_7 j2 i/o 7 io_l11p_7 io_l11p_7 j3 i/o 7 io_l12n_7 io_l12n_7 k9 i/o 7 io_l12p_7 io_l12p_7 j8 i/o 7 io_l13n_7 io_l13n_7 k7 i/o 7 io_l13p_7 io_l13p_7 k8 i/o 7 io_l14n_7 io_l14n_7 k5 i/o 7 io_l14p_7 io_l14p_7 k6 i/o 7 io_l15n_7 io_l15n_7 k3 i/o 7 io_l15p_7 io_l15p_7 k4 i/o 7 io_l16n_7 io_l16n_7 k1 i/o 7 io_l16p_7/ vref_7 io_l16p_7/ vref_7 k2 vref 7 io_l17n_7 io_l17n_7 l9 i/o 7 io_l17p_7 io_l17p_7 l10 i/o 7 io_l19n_7/ vref_7 io_l19n_7/ vref_7 l1 vref 7 io_l19p_7 io_l19p_7 l2 i/o 7 io_l20n_7 io_l20n_7 m10 i/o 7 io_l20p_7 io_l20p_7 m11 i/o table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 95 product specification 1-800-255-7778 r 7 io_l21n_7 io_l21n_7 m7 i/o 7 io_l21p_7 io_l21p_7 m8 i/o 7 io_l22n_7 io_l22n_7 m5 i/o 7 io_l22p_7 io_l22p_7 m6 i/o 7 io_l23n_7 io_l23n_7 m3 i/o 7 io_l23p_7 io_l23p_7 m4 i/o 7 io_l24n_7 io_l24n_7 n10 i/o 7 io_l24p_7 io_l24p_7 m9 i/o 7 io_l25n_7 io_l25n_7 n3 i/o 7 io_l25p_7 io_l25p_7 n4 i/o 7 io_l26n_7 io_l26n_7 p11 i/o 7 io_l26p_7 io_l26p_7 n11 i/o 7 io_l27n_7 io_l27n_7 p7 i/o 7 io_l27p_7/ vref_7 io_l27p_7/ vref_7 p8 vref 7 io_l28n_7 io_l28n_7 p5 i/o 7 io_l28p_7 io_l28p_7 p6 i/o 7 io_l29n_7 io_l29n_7 p3 i/o 7 io_l29p_7 io_l29p_7 p4 i/o 7 io_l30n_7 io_l30n_7 r6 i/o 7 io_l30p_7 io_l30p_7 r7 i/o 7 io_l31n_7 io_l31n_7 r3 i/o 7 io_l31p_7 io_l31p_7 r4 i/o 7 io_l32n_7 io_l32n_7 r1 i/o 7 io_l32p_7 io_l32p_7 r2 i/o 7 io_l33n_7 io_l33n_7 t10 i/o 7 io_l33p_7 io_l33p_7 r9 i/o 7 io_l34n_7 io_l34n_7 t6 i/o 7 io_l34p_7 io_l34p_7 t7 i/o 7 io_l35n_7 io_l35n_7 t2 i/o 7 io_l35p_7 io_l35p_7 t3 i/o 7 io_l37n_7 io_l37n_7 u7 i/o 7 io_l37p_7/ vref_7 io_l37p_7/ vref_7 u8 vref 7 io_l38n_7 io_l38n_7 u5 i/o 7 io_l38p_7 io_l38p_7 u6 i/o 7 io_l39n_7 io_l39n_7 u3 i/o 7 io_l39p_7 io_l39p_7 u4 i/o 7 io_l40n_7/ vref_7 io_l40n_7/ vref_7 u1 vref 7 io_l40p_7 io_l40p_7 u2 i/o 7 n.c. ( ? ) io_l41n_7 g3 i/o ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type 7 n.c. ( ? ) io_l41p_7 g4 i/o 7 n.c. ( ? ) io_l44n_7 l6 i/o 7 n.c. ( ? ) io_l44p_7 l7 i/o 7 io_l45n_7 io_l45n_7 m1 i/o 7 io_l45p_7 io_l45p_7 m2 i/o 7 io_l46n_7 io_l46n_7 n7 i/o 7 io_l46p_7 io_l46p_7 n8 i/o 7 n.c. ( ? ) io_l47n_7 p9 i/o 7 n.c. ( ? ) io_l47p_7 p10 i/o 7 io_l49n_7 io_l49n_7 p1 i/o 7 io_l49p_7 io_l49p_7 p2 i/o 7 io_l50n_7 io_l50n_7 r10 i/o 7 io_l50p_7 io_l50p_7 r11 i/o 7 n.c. ( ? ) io_l51n_7 u11 i/o 7 n.c. ( ? ) io_l51p_7 t11 i/o 7 vcco_7 vcco_7 d3 vcco 7 vcco_7 vcco_7 h3 vcco 7 vcco_7 vcco_7 h7 vcco 7 vcco_7 vcco_7 l4 vcco 7 vcco_7 vcco_7 l8 vcco 7 vcco_7 vcco_7 n12 vcco 7 vcco_7 vcco_7 n2 vcco 7 vcco_7 vcco_7 n6 vcco 7 vcco_7 vcco_7 p12 vcco 7 vcco_7 vcco_7 r12 vcco 7 vcco_7 vcco_7 r8 vcco 7 vcco_7 vcco_7 t12 vcco 7 vcco_7 vcco_7 t4 vcco n/a gnd gnd a1 gnd n/a gnd gnd a13 gnd n/a gnd gnd a16 gnd n/a gnd gnd a19 gnd n/a gnd gnd a2 gnd n/a gnd gnd a22 gnd n/a gnd gnd a26 gnd n/a gnd gnd a30 gnd n/a gnd gnd a33 gnd n/a gnd gnd a34 gnd n/a gnd gnd a5 gnd n/a gnd gnd a9 gnd n/a gnd gnd aa14 gnd table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 96 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r n/a gnd gnd aa15 gnd n/a gnd gnd aa16 gnd n/a gnd gnd aa17 gnd n/a gnd gnd aa18 gnd n/a gnd gnd aa19 gnd n/a gnd gnd aa20 gnd n/a gnd gnd aa21 gnd n/a gnd gnd ab1 gnd n/a gnd gnd ab17 gnd n/a gnd gnd ab18 gnd n/a gnd gnd ab26 gnd n/a gnd gnd ab30 gnd n/a gnd gnd ab34 gnd n/a gnd gnd ab5 gnd n/a gnd gnd ab9 gnd n/a gnd gnd ad3 gnd n/a gnd gnd ad32 gnd n/a gnd gnd ae10 gnd n/a gnd gnd ae25 gnd n/a gnd gnd af1 gnd n/a gnd gnd af13 gnd n/a gnd gnd af16 gnd n/a gnd gnd af19 gnd n/a gnd gnd af22 gnd n/a gnd gnd af30 gnd n/a gnd gnd af34 gnd n/a gnd gnd af5 gnd n/a gnd gnd ah28 gnd n/a gnd gnd ah7 gnd n/a gnd gnd ak1 gnd n/a gnd gnd ak13 gnd n/a gnd gnd ak16 gnd n/a gnd gnd ak19 gnd n/a gnd gnd ak22 gnd n/a gnd gnd ak26 gnd n/a gnd gnd ak30 gnd n/a gnd gnd ak34 gnd n/a gnd gnd ak5 gnd n/a gnd gnd ak9 gnd n/a gnd gnd am11 gnd n/a gnd gnd am24 gnd ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type n/a gnd gnd am3 gnd n/a gnd gnd am32 gnd n/a gnd gnd an1 gnd n/a gnd gnd an2 gnd n/a gnd gnd an33 gnd n/a gnd gnd an34 gnd n/a gnd gnd ap1 gnd n/a gnd gnd ap13 gnd n/a gnd gnd ap16 gnd n/a gnd gnd ap19 gnd n/a gnd gnd ap2 gnd n/a gnd gnd ap22 gnd n/a gnd gnd ap26 gnd n/a gnd gnd ap30 gnd n/a gnd gnd ap33 gnd n/a gnd gnd ap34 gnd n/a gnd gnd ap5 gnd n/a gnd gnd ap9 gnd n/a gnd gnd b1 gnd n/a gnd gnd b2 gnd n/a gnd gnd b33 gnd n/a gnd gnd b34 gnd n/a gnd gnd c11 gnd n/a gnd gnd c24 gnd n/a gnd gnd c3 gnd n/a gnd gnd c32 gnd n/a gnd gnd e1 gnd n/a gnd gnd e13 gnd n/a gnd gnd e16 gnd n/a gnd gnd e19 gnd n/a gnd gnd e22 gnd n/a gnd gnd e26 gnd n/a gnd gnd e30 gnd n/a gnd gnd e34 gnd n/a gnd gnd e5 gnd n/a gnd gnd e9 gnd n/a gnd gnd g28 gnd n/a gnd gnd g7 gnd n/a gnd gnd j1 gnd n/a gnd gnd j13 gnd n/a gnd gnd j16 gnd table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 97 product specification 1-800-255-7778 r n/a gnd gnd j19 gnd n/a gnd gnd j22 gnd n/a gnd gnd j30 gnd n/a gnd gnd j34 gnd n/a gnd gnd j5 gnd n/a gnd gnd k10 gnd n/a gnd gnd k25 gnd n/a gnd gnd l3 gnd n/a gnd gnd l32 gnd n/a gnd gnd n1 gnd n/a gnd gnd n17 gnd n/a gnd gnd n18 gnd n/a gnd gnd n26 gnd n/a gnd gnd n30 gnd n/a gnd gnd n34 gnd n/a gnd gnd n5 gnd n/a gnd gnd n9 gnd n/a gnd gnd p14 gnd n/a gnd gnd p15 gnd n/a gnd gnd p16 gnd n/a gnd gnd p17 gnd n/a gnd gnd p18 gnd n/a gnd gnd p19 gnd n/a gnd gnd p20 gnd n/a gnd gnd p21 gnd n/a gnd gnd r14 gnd n/a gnd gnd r15 gnd n/a gnd gnd r16 gnd n/a gnd gnd r17 gnd n/a gnd gnd r18 gnd n/a gnd gnd r19 gnd n/a gnd gnd r20 gnd n/a gnd gnd r21 gnd n/a gnd gnd t1 gnd n/a gnd gnd t14 gnd n/a gnd gnd t15 gnd n/a gnd gnd t16 gnd n/a gnd gnd t17 gnd n/a gnd gnd t18 gnd n/a gnd gnd t19 gnd n/a gnd gnd t20 gnd ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type n/a gnd gnd t21 gnd n/a gnd gnd t26 gnd n/a gnd gnd t30 gnd n/a gnd gnd t34 gnd n/a gnd gnd t5 gnd n/a gnd gnd t9 gnd n/a gnd gnd u13 gnd n/a gnd gnd u14 gnd n/a gnd gnd u15 gnd n/a gnd gnd u16 gnd n/a gnd gnd u17 gnd n/a gnd gnd u18 gnd n/a gnd gnd u19 gnd n/a gnd gnd u20 gnd n/a gnd gnd u21 gnd n/a gnd gnd u22 gnd n/a gnd gnd v13 gnd n/a gnd gnd v14 gnd n/a gnd gnd v15 gnd n/a gnd gnd v16 gnd n/a gnd gnd v17 gnd n/a gnd gnd v18 gnd n/a gnd gnd v19 gnd n/a gnd gnd v20 gnd n/a gnd gnd v21 gnd n/a gnd gnd v22 gnd n/a gnd gnd w1 gnd n/a gnd gnd w14 gnd n/a gnd gnd w15 gnd n/a gnd gnd w16 gnd n/a gnd gnd w17 gnd n/a gnd gnd w18 gnd n/a gnd gnd w19 gnd n/a gnd gnd w20 gnd n/a gnd gnd w21 gnd n/a gnd gnd w26 gnd n/a gnd gnd w30 gnd n/a gnd gnd w34 gnd n/a gnd gnd w5 gnd n/a gnd gnd w9 gnd n/a gnd gnd y14 gnd table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions 98 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r n/a gnd gnd y15 gnd n/a gnd gnd y16 gnd n/a gnd gnd y17 gnd n/a gnd gnd y18 gnd n/a gnd gnd y19 gnd n/a gnd gnd y20 gnd n/a gnd gnd y21 gnd n/a n.c. ( ? ) n.c. ( ? ) ak31 n.c. n/a vccaux vccaux ad30 vccaux n/a vccaux vccaux ad5 vccaux n/a vccaux vccaux ag16 vccaux n/a vccaux vccaux ag19 vccaux n/a vccaux vccaux aj30 vccaux n/a vccaux vccaux aj5 vccaux n/a vccaux vccaux ak11 vccaux n/a vccaux vccaux ak15 vccaux n/a vccaux vccaux ak20 vccaux n/a vccaux vccaux ak24 vccaux n/a vccaux vccaux ak29 vccaux n/a vccaux vccaux ak6 vccaux n/a vccaux vccaux e11 vccaux n/a vccaux vccaux e15 vccaux n/a vccaux vccaux e20 vccaux n/a vccaux vccaux e24 vccaux n/a vccaux vccaux e29 vccaux n/a vccaux vccaux e6 vccaux n/a vccaux vccaux f30 vccaux n/a vccaux vccaux f5 vccaux n/a vccaux vccaux h16 vccaux n/a vccaux vccaux h19 vccaux n/a vccaux vccaux l30 vccaux n/a vccaux vccaux l5 vccaux n/a vccaux vccaux r30 vccaux n/a vccaux vccaux r5 vccaux n/a vccaux vccaux t27 vccaux n/a vccaux vccaux t8 vccaux n/a vccaux vccaux w27 vccaux n/a vccaux vccaux w8 vccaux n/a vccaux vccaux y30 vccaux n/a vccaux vccaux y5 vccaux n/a vccint vccint aa13 vccint ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type n/a vccint vccint aa22 vccint n/a vccint vccint ab13 vccint n/a vccint vccint ab14 vccint n/a vccint vccint ab15 vccint n/a vccint vccint ab16 vccint n/a vccint vccint ab19 vccint n/a vccint vccint ab20 vccint n/a vccint vccint ab21 vccint n/a vccint vccint ab22 vccint n/a vccint vccint ac12 vccint n/a vccint vccint ac17 vccint n/a vccint vccint ac18 vccint n/a vccint vccint ac23 vccint n/a vccint vccint m12 vccint n/a vccint vccint m17 vccint n/a vccint vccint m18 vccint n/a vccint vccint m23 vccint n/a vccint vccint n13 vccint n/a vccint vccint n14 vccint n/a vccint vccint n15 vccint n/a vccint vccint n16 vccint n/a vccint vccint n19 vccint n/a vccint vccint n20 vccint n/a vccint vccint n21 vccint n/a vccint vccint n22 vccint n/a vccint vccint p13 vccint n/a vccint vccint p22 vccint n/a vccint vccint r13 vccint n/a vccint vccint r22 vccint n/a vccint vccint t13 vccint n/a vccint vccint t22 vccint n/a vccint vccint u12 vccint n/a vccint vccint u23 vccint n/a vccint vccint v12 vccint n/a vccint vccint v23 vccint n/a vccint vccint w13 vccint n/a vccint vccint w22 vccint n/a vccint vccint y13 vccint n/a vccint vccint y22 vccint vccaux cclk cclk al31 config vccaux done done ad24 config table 37: fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 99 product specification 1-800-255-7778 r user i/os by bank ta b l e 3 8 indicates how the available user-i/o pins are dis- tributed between the eight i/o banks for the xc3s4000 in the fg1156 package. similarly, ta bl e 3 9 shows how the available user-i/o pins are distributed between the eight i/o banks for the xc3s5000 in the fg1156 package. vccaux hswap_en hswap_en l11 config vccaux m0 m0 al4 config vccaux m1 m1 ak4 config vccaux m2 m2 ag8 config vccaux prog_b prog_b d4 config vccaux tck tck d31 jtag vccaux tdi tdi e4 jtag vccaux tdo tdo e31 jtag vccaux tms tms h27 jtag ta bl e 3 7 : fg1156 package pinout (continued) bank xc3s4000 pin name xc3s5000 pin name fg1156 pin number type ta bl e 3 8 : user i/os per bank for xc3s4000 in fg1156 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 90 79 0 2 7 2 1 90 79 0 2 7 2 right 2 88 80 0 2 6 0 3 88 79 0 2 7 0 bottom 4 90 73 6 2 7 2 5 90 73 6 2 7 2 left 6 88 79 0 2 7 0 7 88 79 0 2 7 0 ta bl e 3 9 : user i/os per bank for xc3s5000 in fg1156 package package edge i/o bank maximum i/o all possible i/o pins by type i/o dual dci vref gclk to p 0 100 89 0 2 7 2 1 100 89 0 2 7 2 right 2 96 87 0 2 7 0 3 96 87 0 2 7 0 bottom 4 100 83 6 2 7 2 5 100 83 6 2 7 2 left 6 96 87 0 2 7 0 7 96 87 0 2 7 0
spartan-3 fpga family: pinout descriptions 100 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r fg1156 footprint top left corner of package (top view) xc3s4000 (712 max. user i/o) 621 i/o: unrestricted, general-purpose user i/o 55 vref: user i/o or input voltage reference for bank 73 n.c.: unconnected pins for xc3s4000 ( ? ) xc3s5000 (784 max. user i/o) 692 i/o: unrestricted, general-purpose user i/o 56 vref: user i/o or input voltage reference for bank 1 n.c.: unconnected pins for xc3s5000 ( ? ) figure 16: fg1156 package footprint (top view) gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o l01p_0 vrn_0 i/o l02p_0 i/o l05p_0 vref_0 i/o l34p_0 i/o l36p_0 i/o l38p_0 i/o l40p_0 i/o l15p_0 i/o l22p_0 i/o l26p_0 vref_0 i/o l32p_0 gclk6 i/o l01n_0 vrp_0 i/o l02n_0 i/o l03p_0 i/o l05n_0 i/o l34n_0 i/o l36n_0 i/o i/o l38n_0 i/o l40n_0 i/o l15n_0 vcco_0 i/o l22n_0 i/o l26n_0 i/o l28p_0 i/o l32n_0 gclk7 i/o l01n_7 vrp_7 i/o l01p_7 vrn_7 vcco_0 i/o l03n_0 i/o l04p_0 i/o l33p_0 vcco_0 i/o l08p_0 i/o l37p_0 i/o l14p_0 i/o l17p_0 i/o l21p_0 i/o l25p_0 i/o l28n_0 i/o l31p_0 vref_0 i/o l02n_7 i/o l02p_7 vcco_7 prog_b io vref_0 i/o l04n_0 i/o l33n_0 i/o l35p_0 i/o l08n_0 i/o l37n_0 vcco_0 i/o l14n_0 i/o l17n_0 i/o l21n_0 i/o l25n_0 vcco_0 i/o l31n_0 i/o l03n_7 vref_7 i/o l03p_7 tdi vccaux i/o l06p_0 i/o l35n_0 io vref_0 vccaux i/o l13p_0 i/o l20p_0 vccaux i/o i/o l05n_7 i/o l05p_7 i/o l04n_7 i/o l04p_7 vccaux i/o i/o l06n_0 i/o i/o l07p_0 i/o l10p_0 i/o l39p_0 i/o l13n_0 vcco_0 i/o l20n_0 i/o l24p_0 i/o l27p_0 i/o l30p_0 i/o i/o i/o l41n_7 i/o l41p_7 i/o l06n_7 i/o l06p_7 vcco_0 i/o l07n_0 i/o l10n_0 i/o l39n_0 i/o i/o l16p_0 i/o l19p_0 i/o l24n_0 i/o l27n_0 i/o l30n_0 i/o l08n_7 i/o l08p_7 vcco_7 i/o l10p_7 vref_7 i/o l07n_7 i/o l07p_7 vcco_7 i/o i/o i/o l09p_0 vcco_0 i/o l12p_0 i/o l16n_0 i/o l19n_0 vcco_0 vccaux i/o l29p_0 i/o l11n_7 i/o l11p_7 i/o l10n_7 i/o l09n_7 i/o l09p_7 i/o l12p_7 i/o i/o l09n_0 i/o i/o l12n_0 io vref_0 i/o l23p_0 i/o l29n_0 i/o l16n_7 i/o l16p_7 vref_7 i/o l15n_7 i/o l15p_7 i/o l14n_7 i/o l14p_7 i/o l13n_7 i/o l13p_7 i/o l12n_7 i/o i/o l11p_0 i/o i/o l18p_0 i/o l23n_0 i/o i/o i/o l19n_7 vref_7 i/o l19p_7 vcco_7 vccaux i/o l44n_7 i/o l44p_7 vcco_7 i/o l17n_7 i/o l17p_7 hswap_ en i/o l11n_0 i/o i/o l18n_0 io vref_0 i/o i/o i/o l45n_7 i/o l45p_7 i/o l23n_7 i/o l23p_7 i/o l22n_7 i/o l22p_7 i/o l21n_7 i/o l21p_7 i/o l24p_7 i/o l20n_7 i/o l20p_7 vccint vcco_0 vcco_0 vcco_0 vcco_0 vccint vcco_7 i/o l25n_7 i/o l25p_7 vcco_7 i/o l46n_7 i/o l46p_7 i/o l24n_7 i/o l26p_7 vcco_7 vccint vccint vccint vccint i/o l49n_7 i/o l49p_7 i/o l29n_7 i/o l29p_7 i/o l28n_7 i/o l28p_7 i/o l27n_7 i/o l27p_7 vref_7 i/o l47n_7 i/o l47p_7 i/o l26n_7 vcco_7 vccint i/o l32n_7 i/o l32p_7 i/o l31n_7 i/o l31p_7 vccaux i/o l30n_7 i/o l30p_7 vcco_7 i/o l33p_7 i/o l50n_7 i/o l50p_7 vcco_7 vccint i/o l35n_7 i/o l35p_7 vcco_7 i/o l34n_7 i/o l34p_7 vccaux i/o l33n_7 i/o l51p_7 vcco_7 vccint i/o l40n_7 vref_7 i/o l40p_7 i/o l39n_7 i/o l39p_7 i/o l38n_7 i/o l38p_7 i/o l37n_7 i/o l37p_7 vref_7 i/o i/o i/o l51n_7 ? ? ? ?? ?? ?? ? ? ? ? ? ? ? ? ? vccint 10 11 12 13 14 15 16 17 123456789 bank 0 a b c d e f g h j k l m n p r t u bank 7 ds099-4_14a_072903
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 101 product specification 1-800-255-7778 r all devices top right corner of package (top view) 12 dual: configuration pin, then possible user i/o 16 dci: user i/o or reference resistor input for bank 8 gclk: user i/o or global clock buffer input 7 config: dedicated configuration pins 4 jtag: dedicated jtag port pins 104 vcco: output voltage supply for bank 40 vccint: internal core voltage supply (+1.2v) 32 vccaux: auxiliary voltage supply (+2.5v) 184 gnd: ground 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bank 1 a b c d e f g h j k l m n p r t u bank 2 i/o i/o l40n_1 i/o l26n_1 i/o l19n_1 i/o l15n_1 i/o l14n_1 i/o l08n_1 i/o l34n_1 i/o l05n_1 i/o l02n_1 i/o l01n_1 vrp_1 i/o l32n_1 gclk5 i/o l28n_1 i/o l40p_1 i/o l26p_1 vcco_1 i/o l19p_1 i/o l15p_1 i/o l14p_1 i/o i/o l08p_1 i/o l34p_1 i/o l05p_1 i/o l03n_1 i/o l02p_1 i/o l01p_1 vrn_1 i/o l32p_1 gclk4 i/o l28p_1 i/o l39n_1 i/o l25n_1 i/o l22n_1 i/o i/o l13n_1 i/o l10n_1 vref_1 vcco_1 i/o l33n_1 i/o l04n_1 i/o l03p_1 vcco_1 i/o l01n_2 vrp_2 i/o l01p_2 vrn_2 i/o l31n_1 vref_1 vcco_1 i/o l39p_1 i/o l25p_1 i/o l22p_1 i/o l18n_1 vcco_1 i/o l13p_1 i/o l10p_1 i/o l07n_1 i/o l33p_1 i/o l04p_1 io vref_1 vcco_2 i/o l02n_2 i/o l02p_2 i/o l31p_1 vccaux i/o i/o l18p_1 vccaux i/o i/o l07p_1 i/o l06n_1 vref_1 vccaux gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd tdo tck i/o l03n_2 vref_2 i/o l03p_2 i/o i/o l27n_1 i/o l38n_1 i/o l24n_1 vcco_1 i/o l17n_1 vref_1 i/o l36n_1 i/o l12n_1 i/o l09n_1 i/o i/o l06p_1 i/o vccaux i/o l04n_2 i/o l04p_2 i/o l41n_2 i/o l41p_2 i/o l30n_1 i/o l27p_1 i/o l38p_1 i/o l24p_1 i/o l21n_1 i/o l17p_1 i/o l36p_1 i/o l12p_1 i/o l09p_1 vcco_1 i/o l05n_2 i/o l05p_2 i/o l42n_2 i/o l42p_2 i/o i/o i/o l30p_1 vccaux vcco_1 i/o l23n_1 i/o l21p_1 i/o vcco_1 i/o l11n_1 i/o tms vcco_2 i/o l06n_2 i/o l06p_2 i/o l09n_2 vref_2 vcco_2 i/o l07n_2 i/o l07p_2 i/o l29n_1 i/o l37n_1 i/o l23p_1 i/o l16n_1 i/o l35n_1 i/o l11p_1 i/o i/o l11n_2 i/o l08n_2 i/o l08p_2 i/o l09p_2 i/o l10n_2 i/o l10p_2 i/o l29p_1 i/o i/o l37p_1 io vref_1 i/o l20n_1 i/o l16p_1 i/o l35p_1 i/o l11p_2 i/o l12n_2 i/o l12p_2 i/o l13n_2 i/o l13p_2 vref_2 i/o l14n_2 i/o l14p_2 i/o l15n_2 i/o l15p_2 io vref_1 i/o i/o i/o i/o l20p_1 i/o i/o i/o l16n_2 i/o l16p_2 vcco_2 i/o l17n_2 i/o l17p_2 vref_2 vccaux vcco_2 i/o l45n_2 i/o l45p_2 vccint vcco_1 vcco_1 vcco_1 vcco_1 vccint i/o l46n_2 i/o l46p_2 i/o l21n_2 i/o l47n_2 i/o l47p_2 i/o l19n_2 i/o l19p_2 i/o l20n_2 i/o l20p_2 i/o l48n_2 i/o l48p_2 vccint vccint vccint vccint vcco_2 i/o l24n_2 i/o l21p_2 i/o l22n_2 i/o l22p_2 vcco_2 i/o l23n_2 vref_2 i/o l23p_2 vcco_2 vccint vcco_2 i/o l24p_2 i/o l49n_2 i/o l49p_2 i/o l50n_2 i/o l50p_2 i/o l26n_2 i/o l26p_2 i/o l27n_2 i/o l27p_2 i/o l28n_2 i/o l28p_2 vccint vcco_2 i/o l29n_2 i/o l29p_2 i/o l33n_2 vcco_2 i/o l30n_2 i/o l30p_2 vccaux i/o l31n_2 i/o l31p_2 i/o l32n_2 i/o l32p_2 vccint vcco_2 i/o l51n_2 i/o l33p_2 vccaux i/o l34n_2 vref_2 i/o l34p_2 vcco_2 i/o l35n_2 i/o l35p_2 vccint i/o l51p_2 ?? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? i/o i/o i/o l37n_2 i/o l37p_2 i/o l38n_2 i/o l38p_2 i/o l39n_2 i/o l39p_2 i/o l40n_2 i/o l40p_2 vref_2 ds099-4_14b_072903
spartan-3 fpga family: pinout descriptions 102 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r bottom left corner of package (top view) i/o l40p_6 vref_6 i/o l40n_6 i/o l39p_6 i/o l39n_6 i/o l38p_6 i/o l38n_6 i/o l52p_6 i/o l52n_6 i/o i/o i/o l49p_6 vccint i/o l37p_6 i/o l37n_6 vcco_6 i/o l36p_6 i/o l36n_6 vccaux i/o l35p_6 i/o l49n_6 vcco_6 vccint i/o l34p_6 i/o l34n_6 vref_6 i/o l33p_6 i/o l33n_6 vccaux i/o l48p_6 i/o l48n_6 vcco_6 i/o l35n_6 i/o l32p_6 i/o l32n_6 vcco_6 vccint i/o l31p_6 i/o l31n_6 i/o l30p_6 i/o l30n_6 i/o l29p_6 i/o l29n_6 i/o l28p_6 i/o l28n_6 i/o l46p_6 i/o l46n_6 i/o l27p_6 vcco_6 vccint vcco_6 i/o l26p_6 i/o l26n_6 vcco_6 i/o l25p_6 i/o l25n_6 i/o l24p_6 i/o l27n_6 vcco_6 vccint vccint vccint vccint i/o l23p_6 i/o l23n_6 i/o l45p_6 i/o l45n_6 i/o l22p_6 i/o l22n_6 i/o l21p_6 i/o l21n_6 i/o l24n_6 vref_6 i/o l20p_6 i/o l20n_6 vccint vcco_5 vcco_5 vcco_5 vcco_5 vccint i/o l19p_6 i/o l19n_6 vcco_6 vccaux i/o l44p_6 i/o l44n_6 vcco_6 i/o l17p_6 vref_6 i/o l17n_6 i/o i/o i/o l16p_5 i/o i/o i/o i/o i/o l16p_6 i/o l16n_6 i/o l15p_6 i/o l15n_6 i/o l14p_6 i/o l14n_6 i/o l13p_6 vref_6 i/o l13n_6 i/o l12p_6 i/o l39p_5 i/o l12p_5 i/o l16n_5 i/o i/o l23p_5 i/o i/o l29p_5 vref_5 i/o l11p_6 i/o l11n_6 i/o l10p_6 i/o l09p_6 i/o l09n_6 vref_6 i/o l12n_6 i/o i/o l07p_5 i/o l39n_5 i/o l12n_5 i/o l19p_5 vref_5 i/o l23n_5 i/o l29n_5 i/o l08p_6 i/o l08n_6 vcco_6 i/o l10n_6 i/o l07p_6 i/o l07n_6 vcco_6 m2 i/o i/o l07n_5 vcco_5 i/o i/o l17p_5 i/o l19n_5 vcco_5 vccaux i/o l30p_5 i/o i/o i/o l41p_6 i/o l41n_6 i/o l06p_6 i/o l06n_6 vcco_5 i/o l37p_5 i/o l08p_5 i/o l40p_5 i/o l13p_5 i/o l17n_5 i/o l20p_5 i/o l24p_5 i/o l27p_5 i/o l30n_5 i/o l05p_6 i/o l05n_6 i/o l04p_6 i/o l04n_6 vccaux i/o i/o l06p_5 io vref_5 i/o l37n_5 i/o l08n_5 i/o l40n_5 i/o l13n_5 vcco_5 i/o l20n_5 i/o l24n_5 i/o l27n_5 vref_5 i/o i/o l03p_6 i/o l03n_6 vref_6 m1 vccaux i/o l06n_5 i/o l35p_5 i/o vccaux i/o l14p_5 i/o vccaux i/o l31p_5 d5 i/o l02p_6 i/o l02n_6 vcco_6 m0 io vref_5 i/o l04p_5 i/o l33p_5 i/o l35n_5 i/o l38p_5 i/o l09p_5 vcco_5 i/o l14n_5 i/o l18p_5 i/o l21p_5 i/o l25p_5 vcco_5 i/o l31n_5 d4 i/o l01p_6 vrn_6 i/o l01n_6 vrp_6 vcco_5 i/o l03p_5 i/o l04n_5 i/o l33n_5 vcco_5 i/o l38n_5 i/o l09n_5 i/o i/o l18n_5 i/o l21n_5 i/o l25n_5 i/o l28p_5 d7 i/o l32p_5 gclk2 i/o l01p_5 cs_b i/o l02p_5 i/o l03n_5 i/o l05p_5 i/o l34p_5 i/o l36p_5 i/o i/o l10p_5 vrn_5 i/o l11p_5 i/o l15p_5 vcco_5 i/o l22p_5 i/o l26p_5 i/o l28n_5 d6 i/o l32n_5 gclk3 i/o l01n_5 rdwr_b i/o l02n_5 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd i/o l05n_5 i/o l34n_5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i/o l36n_5 i/o l10n_5 vrp_5 i/o l11n_5 vref_5 i/o l15n_5 i/o l22n_5 i/o l26n_5 io vref_5 bank 5 10 11 12 13 14 15 16 17 v w y a a a b a c a d a e a f a g a h a j a k a l a m a n a p bank 6 123456789 ds099-4_14c_072503
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 103 product specification 1-800-255-7778 r bottom right corner of package (top view) vccint i/o l51n_3 i/o i/o i/o l37p_3 i/o l37n_3 i/o l38p_3 i/o l38n_3 i/o l39p_3 i/o l39n_3 i/o l40p_3 i/o l40n_3 vref_3 vccint vcco_3 i/o l51p_3 i/o l33n_3 vccaux i/o l34p_3 vref_3 i/o l34n_3 vcco_3 i/o l35p_3 i/o l35n_3 vccint vcco_3 i/o l50p_3 i/o l50n_3 i/o l33p_3 vcco_3 i/o l30p_3 i/o l30n_3 vccaux i/o l31p_3 i/o l31n_3 i/o l32p_3 i/o l32n_3 vccint vcco_3 i/o l48n_3 i/o l49p_3 i/o l49n_3 i/o l26p_3 i/o l26n_3 i/o l27p_3 i/o l27n_3 i/o l28p_3 i/o l28n_3 i/o l29p_3 i/o l29n_3 vccint vccint vccint vccint vcco_3 i/o l48p_3 i/o l24n_3 i/o l46p_3 i/o l46n_3 vcco_3 i/o l47p_3 i/o l47n_3 vcco_3 vccint vcco_4 vcco_4 vcco_4 vcco_4 vccint i/o l20p_3 i/o l20n_3 i/o l24p_3 i/o l21p_3 i/o l21n_3 i/o l22p_3 i/o l22n_3 i/o l23p_3 vref_3 i/o l23n_3 i/o l45p_3 i/o l45n_3 i/o i/o i/o i/o l18n_4 i/o i/o l11n_4 done i/o l17p_3 vref_3 i/o l17n_3 vcco_3 i/o l44p_3 i/o l44n_3 vcco_3 i/o l19p_3 i/o l19n_3 i/o i/o i/o l23n_4 i/o l18p_4 i/o i/o l11p_4 i/o i/o l12n_3 i/o l13p_3 i/o l13n_3 vref_3 i/o l14p_3 i/o l14n_3 i/o l15p_3 i/o l15n_3 i/o l16p_3 i/o l16n_3 i/o l29n_4 i/o l23p_4 io vref_4 i/o l12n_4 i/o i/o l07n_4 i/o i/o l12p_3 i/o l09p_3 vref_3 i/o l09n_3 i/o l10n_3 i/o l11p_3 i/o l11n_3 i/o l29p_4 vccaux vcco_4 i/o l19n_4 i/o l16n_4 i/o l12p_4 vcco_4 i/o l07p_4 i/o i/o vcco_3 i/o l07p_3 i/o l07n_3 i/o l10p_3 vcco_3 i/o l08p_3 i/o l08n_3 i/o l30n_4 d2 i/o l27n_4 din d0 i/o l24n_4 i/o l19p_4 i/o l16p_4 io vref_4 i/o l39n_4 i/o l08n_4 i/o l05n_4 vcco_4 i/o l06p_3 i/o l06n_3 i/o l41p_3 i/o l41n_3 i/o i/o i/o l30p_4 d3 i/o l27p_4 d1 i/o l24p_4 i/o l20n_4 vcco_4 i/o l13n_4 i/o l39p_4 i/o l08p_4 i/o l05p_4 i/o i/o l35n_4 i/o vccaux i/o l04p_3 i/o l04n_3 i/o l05p_3 i/o l05n_3 io vref_4 vccaux i/o l20p_4 i/o l13p_4 vccaux i/o i/o l38n_4 i/o l35p_4 vccaux n.c. i/o l03p_3 i/o l03n_3 i/o l31n_4 init_b vcco_4 i/o l25n_4 i/o l21n_4 i/o l17n_4 i/o l14n_4 vcco_4 i/o l09n_4 i/o l06n_4 vref_4 i/o l38p_4 i/o l36n_4 i/o l33n_4 io vref_4 cclk vcco_3 i/o l02p_3 i/o l02n_3 vref_3 i/o l31p_4 dout bus y i/o l28n_4 i/o l25p_4 i/o l21p_4 i/o l17p_4 i/o l14p_4 i/o l09p_4 i/o l06p_4 vcco_4 i/o l36p_4 i/o l33p_4 i/o l03n_4 vcco_4 i/o l01p_3 vrn_3 i/o l01n_3 vrp_3 i/o l32n_4 gclk1 i/o l28p_4 i/o l26n_4 i/o l22n_4 vref_4 vcco_4 i/o l15n_4 i/o l40n_4 i/o l10n_4 i/o i/o l04n_4 i/o l37n_4 i/o l34n_4 i/o l03p_4 i/o l02n_4 i/o l01n_4 vrp_4 i/o l32p_4 gclk0 i/o l26p_4 vref_4 i/o l22p_4 i/o l15p_4 i/o l40p_4 ? ? ? ? ? ? ? ?? ?? ?? ?? ? ? ? ? ? i/o l10p_4 i/o l04p_4 i/o l37p_4 i/o l34p_4 i/o l02p_4 i/o l01p_4 vrn_4 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 bank 4 v w y a a a b a c a d a e a f a g a h a j a k a l a m a n a p bank 3 ds099-4_14d_072903 vccaux
spartan-3 fpga family: pinout descriptions 104 www.xilinx.com ds099-4 (v1.5) july 13, 2004 1-800-255-7778 product specification r revision history date version no. description 04/03/03 1.0 initial xilinx release. 04/21/03 1.1 added information on the vq100 package footprint, including a complete pinout table ( ta bl e 1 6 ) and footprint diagram ( figure 8 ). updated ta b l e 1 5 with final i/o counts for the vq100 package. also added final differential i/o pair counts for the tq144 package. added clarifying comments to hswap_en pin description on page 13 . updated the footprint diagram for the fg900 package shown in figure 15a and figure 15b . some thick lines separating i/o banks were incorrect. made cosmetic changes to figure 1 , figure 3 , and figure 4 . updated xilinx hypertext links. added xc3s200 and xc3s400 to pin name column in ta b l e 1 8 . 05/12/03 1.1.1 am32 pin was missing gnd label in fg1156 package diagram ( figure 16 ). 07/11/03 1.1.2 corrected misspellings of gclk in ta b l e 1 and ta bl e 2 . changed cmos25 to lvcmos25 in dual-purpose pin i/o standard during configuration section. clarified references to module 2. for xc3s5000 in fg1156 package, corr ected n.c. symbol to a black square in ta b l e 3 7 , key, and package drawing. 07/29/03 1.2 corrected pin names on fg1156 package. some package balls incorrectly included lvds pair names. the affected balls on the fg1156 package include g1, g2, g33, g34, u9, u10, u25, u26, v9, v10, v25, v26, ah1, ah2, ah33, ah34. the number of lvds pairs is unaffected. modified affected balls and re-sorted rows in ta b l e 3 7 . updated affected balls in figure 16 . also updated ascii and excel electronic versions of fg1156 pinout. 08/19/03 1.2.1 removed 100 mhz configrate option in cclk: configuration clock section and in ta bl e 1 1 . added note that tdo is a totem-pole output in ta b l e 9 . 10/09/03 1.2.2 some pins had incorrect bank designations and were improperly sorted in ta bl e 2 0 . no pin names or functions changed. renamed dci_in to dci and added black diamond to n.c. pins in ta bl e 2 0 . in figure 10 , removed some extraneous text fr om pin 106 and corrected spelling of pins 45, 48, and 81. 12/17/03 1.3 added fg320 pin tables and pinout diagram ( fg320: 320-lead fine-pitch ball grid array ). made cosmetic changes to the tq144 footprint ( figure 9 ), the pq208 footprint ( figure 10 ), the fg676 footprint ( figure 14 ), and the fg900 footprint ( figure 15 ). clarified wording in precautions when using the jtag port in 3.3v environments section. 02/27/04 1.4 clarified wording in using jtag port after configuration section. in ta b l e 1 2 , reduced package height for fg320 and increased maximum i/o values for the fg676, fg900, and fg1156 packages. 07/13/04 1.5 added information on lead-free (pb-free) package options to the package overview section plus ta bl e 1 2 and ta bl e 1 3 . clarified the vrn_# reference resistor requirements for i/o standards that use single termination as described in the dci termination types section and in figure 3b . graduated from advance product specification to product specification.
spartan-3 fpga family: pinout descriptions ds099-4 (v1.5) july 13, 2004 www.xilinx.com 105 product specification 1-800-255-7778 r the spartan-3 family data sheet ds099-1 , spartan-3 fpga family: introduction and ordering information (module 1) ds099-2 , spartan-3 fpga family: functional description (module 2) ds099-3, spartan-3 fpga family: dc and switching characteristics (module 3) ds099-4 , spartan-3 fpga family: pinout descriptions (module 4)

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